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MC100EP52MNR4G

P1-P3P4-P6P7-P9P10-P11
MC10EP52, MC100EP52
www.onsemi.com
7
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Figure 2. F
max
Typical
FREQUENCY (MHz)
V
OUTpp
(mV)
3.3 V
5V
Figure 3. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D
− Termination of ECL Logic Devices)
Driver
Device
Receiver
Device
QD
Q D
Z
o
= 50 W
Z
o
= 50 W
50 W 50 W
V
TT
V
TT
= V
CC
− 2.0 V
MC10EP52, MC100EP52
www.onsemi.com
8
ORDERING INFORMATION
Device Package Shipping
†
MC10EP52DG SOIC−8 NB
(Pb-Free)
98 Units / Tube
MC10EP52DR2G SOIC−8 NB
(Pb-Free)
2500 Tape & Reel
MC10EP52DTG TSSOP−8
(Pb-Free)
100 Units / Tube
MC10EP52DTR2G TSSOP−8
(Pb-Free)
2500 Tape & Reel
MC10EP52MNR4G DFN8
(Pb-Free)
1000 / Tape & Reel
MC100EP52DG SOIC−8 NB
(Pb-Free)
98 Units / Tube
MC100EP52DR2G SOIC−8 NB
(Pb-Free)
2500 Tape & Reel
MC100EP52DTG TSSOP−8
(Pb-Free)
100 Units / Tube
MC100EP52DTR2G TSSOP−8
(Pb-Free)
2500 Tape & Reel
MC100EP52MNR4G DFN8
(Pb-Free)
1000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D
.
Resource Reference of Application Notes
AN1405/D − ECL Clock Distribution Techniques
AN1406/D − Designing with PECL (ECL at +5.0 V)
AN1503/D −
ECLinPSt I/O SPiCE Modeling Kit
AN1504/D − Metastability and the ECLinPS Family
AN1568/D − Interfacing Between LVDS and ECL
AN1672/D − The ECL Translator Guide
AND8001/D − Odd Number Counters Design
AND8002/D − Marking and Date Codes
AND8020/D − Termination of ECL Logic Devices
AND8066/D − Interfacing with ECLinPS
AND8090/D − AC Characteristics of ECL Devices
MC10EP52, MC100EP52
www.onsemi.com
9
PACKAGE DIMENSIONS
SOIC−8 NB
D SUFFIX
CASE 751−07
ISSUE AK
SEATING
PLANE
1
4
58
N
J
X 45
_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
B
S
D
H
C
0.10 (0.004)
DIM
A
MIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.053 0.069
D 0.33 0.51 0.013 0.020
G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
J 0.19 0.25 0.007 0.010
K 0.40 1.27 0.016 0.050
M 0 8 0 8
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) Z
S
X
S
M
____
1.52
0.060
7.0
0.275
0.6
0.024
1.270
0.050
4.0
0.155
ǒ
mm
inches
Ǔ
SCALE 6:1
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
P1-P3P4-P6P7-P9P10-P11

MC100EP52MNR4G

Mfr. #:
Buy MC100EP52MNR4G
Manufacturer:
ON Semiconductor
Description:
Flip Flops BBG ECL FL FLOP DIFF
Lifecycle:
New from this manufacturer.
Delivery:
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