IDT72V8980J8 Datasheet 72V8980JG, 72V8980JG8, 72V8980PVG8 | P4-P6

Commercial Temperature Range

IDT72V8980 3.3V Time Slot Interchange

Digital Switch 256 x 256

Data to be output on the serial streams may come from two sources: Data

Memory or Connection Memory. The Connection Memory is 16 bits wide and

is split into two 8-bit blocks—Connection Memory HIGH and Connection

Memory LOW. Each location in Connection Memory is associated with a

particular channel in the output stream so as to provide a one-to-one correspon-

dence between the two memories. This correspondence allows for per channel

control for each TX output stream. In Processor Mode, data output on the TX

stream is taken from the Connect Memory Low and originates from the

microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is

read from Data Memory using the address in Connection Memory. Data

destined for a particular channel on the serial output stream is read during the

previous channel time slot to allow time for memory access and internal parallel-

to-serial conversion.

CONNECTION MODE

In Connection Mode, the addresses of input source for all output channels

are stored in the Connect Memory Low. The Connect Memory Low locations

are mapped to corresponding 8-bit x 32-channel output. The contents of the

Data Memory at the selected address are then transferred to the parallel-to-

serial converters. By having the output channel to specify the input channel

through the connect memory, input channels can be broadcast to several output

channels.

PROCESSOR MODE

In Processor Mode the CPU writes data to specific Connect Memory Low

locations which are to be output on the TX streams. The contents of the Connect

Memory Low are transferred to the parallel-to-serial converter one channel

before it is to be output and are transmitted each frame to the output until it is

changed by the CPU.

CONTROL

The Connect Memory High bits (Table 4) control the per-channel functions

available in the IDT72V8980. Output channels are selected into specific modes

such as: Processor Mode or Connection mode and Output Drivers Enabled

or in three-state condition. There is also one bit to control the state of the CCO

output pin.

OUTPUT DRIVE ENABLE (ODE)

The ODE pin is the master output control pin. If the ODE input is held LOW

all TDM outputs will be placed in high impedance regardless Connect Memory

High programming. However, if ODE is HIGH, the contents of Connect Memory

High control the output state on a per-channel basis.

DELAY THROUGH THE IDT72V8980

The transfer of information from the input serial streams to the output serial

streams results in a delay through the device. The delay through the IDT72V8980

device varies according to the combination of input and output streams and the

movement within the stream from channel to channel. Data received on an input

stream must first be stored in Data Memory before it is sent out.

As information enters the IDT72V8980 it must first pass through an internal

serial-to-parallel converter. Likewise, before data leaves the device, it must

pass through the internal parallel-to-serial converter. This data preparation has

an effect on the channel positioning in the frame immediately following the

incoming frame—mainly, data cannot leave in the same time slot, on in the time

slot immediately following. Therefore, information that is to be output in the same

channel position as the information is input, relative to the frame pulse, will be

output in the following frame. As well, information switched to the channel

immediately following the input channel will not be output in the time slot

immediately following but in the next timeslot allocated to the output channel, one

frame later.

Whether information can be output during a following timeslot after the

information entered the IDT72V8980 depends on which RX stream the channel

information enters on and which TX stream the information leaves on. This

situation is caused by the order in which input stream information is placed into

Data Memory and the order in which stream information is queued for output.

Table 1 shows the allowable input/output stream combinations for the minimum

2 channel delay.

SOFTWARE CONTROL

If the A5 address line input is LOW then the IDT72V8980 Internal Control

lines are used to select the 32 possible channels per input or output stream. The

address input lines and the Stream Address bits (STA) of the Control register

give the user the capability of selecting all positions of IDT72V8980 Data and

Connection memories. The IDT72V8980 memory mapping is illustrated in

Table 2 and Figure 3.

The data in the control register consists of Memory Select and Stream

Address bits, Split Memory and Processor Mode bits. In Split Memory mode (Bit

7 of the Control register) reads are from the Data Memory and writes are to the

Connect Memory as specified by the Memory Select Bits (Bits 4 and 3 of the

Control Register). The Memory Select bits allow the Connect Memory High or

LOW or the Data Memory to be chosen, and the Stream Address bits define

internal memory subsections corresponding to input or output streams.

The Processor Enable bit (bit 6) places EVERY output channel on every

output stream in Processor Mode; i.e., the contents of the Connect Memory LOW

(CML, see Table 5) are output on the TX output streams once every frame

unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8980

behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connect

Memory High (CMH) locations were set to HIGH, regardless of the actual value.

If PE is LOW, then bit 2 and 0 of each Connect Memory High location operates

normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output

channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of

the CML define the source information (stream and channel) of the time slot that

is to be switched to an output.

Data

Memory

Connection

Memory

5705 drw06

Microprocessor

Receive

Serial Data

Streams

Transmit

Serial Data

Streams

Receive

Serial Data

Streams

5705 drw05

RX TX

Transmit

Serial Data

Streams

Data

Memory

Connection

Memory

Figure 2. Processor Mode

Figure 1. Connection Mode

FUNCTIONAL DESCRIPTION (Cont'd)

Commercial Temperature Range

IDT72V8980 3.3V Time Slot Interchange

Digital Switch 256 x 256

If the ODE input pin is LOW, then all the serial outputs are high-impedance.

If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH)

or disables (if LOW) the output stream and channel.

The contents of bit 1 (CCO) of each Connection Memory High Location (see

Table 4) is output on CCO pin once every frame. The CCO pin is a 2.048 Mb/s

output, which carries 256 bits. If CCO bit is set HIGH, the corresponding bit on

CCO output is transmitted HIGH. If CCO is LOW, the corresponding bit on the

CCO output is transmitted in LOW. The contents of the 256 CCO bits of the CMH

are transmitted sequentially on to the CCO output pin and are synchronous to

the TX streams. To allow for delay in any external control circuitry the contents

of the CCO bit is output one channel before the corresponding channel on the

TX streams. For example, the contents of CCO bit in position 0 (corresponding

to TX0, CH0) is transmitted synchronously with the TX channel 31, bit 7. Bit 1's

of CMH for channel 1 of streams 0-7 are output synchronously with TX channel

0 bits 7-0.

INITIALIZATION OF THE IDT72V8980

On initialization or power up, the contents of the Connection Memory High

can be in any state. This is a potentially hazardous condition when multiple TX

TABLE 2 — ADDRESS MAPPING

Connection Memory High

Connection Memory Low

Channel 0 Channel 1 Channel 2 Channel 31

100001 100010 111111

Data Memory

0 0

0 1

1 3

1 0

0 4

1 0

1 5

1 1

0 6

1 1 1

Stream

0 1

1 1

Control Register

External Address Bits A5-A0

5705 drw07

100000

The Control Register is only accessed when A5=0.

All other address bits have no effect when A5=0.

When A5 =1, only 32 bytes are randomly accessable

via A0-A4 at any one instant. Which 32 bytes are

accessed is determined by the state of CRb0 -CRb4.

The 32 bytes correlate to 32 channel of one ST-BUS

stream.

6CR

5CR

4CR

3CR

2CR

1CR

4CR

2CR

1CR

TABLE 1 — INPUT STREAM TO OUTPUT

STREAM COMBINATIONS THAT CAN

PROVIDE THE MINIMUM 2-CHANNEL

DELAY

Figure 3. Address Mapping

NOTES:

1. Writing to the Control Register is the only fast transaction.

2. Memory and stream are specified by the contents of the Control Register.

A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION

0XXXXX 00-1F Control Register

(1)

100000 20 Channel 0

(2)

100001 21 Channel 1

(2)

•••••• • •

111111 3F Channel 31

(2)

outputs are tied together to form matrices. The ODE pin should be held low on

power up to keep all outputs in the high impedance condition until the contents

of the CMH are programmed.

During the microprocessor initialization routine, the microprocessor should

program the desired active paths through the matrices, and put all other channels

into the high impedance state. Care should be taken that no two connected TX

outputs drive the bus simultaneously. With the CMH setup, the microprocessor

controlling the matrices can bring the ODE signal high to relinquish high

impedance state control to the Connection Memory High bits outputs.

RESET

The reset pin is designed to be used with board reset circuitry. During reset

the TX serial streams will be put into high-impedance and the state of internal

registers and counters will be reset. As the connection memory can be in any

state after a power up, the ODE pin should be used to hold the TX streams in

high-impedance until the per-channel output enable control in the connection

memory high is appropriately programmed. The main difference between ODE

and reset is, reset alters the state of the registers and counters where as ODE

controls only the high-impedance state of the TX streams. RESET input is only

provided on the SSOP package.

Input Output Stream

0 1,2,3,4,5,6,7

1 3,4,5,6,7

2 5,6,7

4 1,2,3,4,5,6,7

5 3,4,5,6,7

6 5,6,7

Commercial Temperature Range

IDT72V8980 3.3V Time Slot Interchange

Digital Switch 256 x 256

TABLE 4 — CONNECTION MEMORY HIGH REGISTER

TABLE 5 — CONNECTION MEMORY LOW REGISTER

TABLE 3 — CONTROL REGISTER CONFIGURATION

Bit Name Description

7 SM (Split Memory) When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except

when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the

operations. In either case, the Stream Address Bits select the subsection of the memory which is made available.

6 PE (Processor Mode) When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE

pin is LOW. When 0, the Connection Memory bits for each channel determine what is output.

5 unused

4-3 MS1-MS0 0-0 - Not to be used.

(Memory Select Bits) 0-1 - Data Memory (read only from the microprocessor port)

1-0 - Connection Memory LOW

1-1 - Connection Memory is HIGH

2-0 STA2-0 The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the

(Stream Address Bits) subsection of memory made accessible for subsequent operations.

76543210

Mode Control Memory Select

Bits (unused) Bits Stream Address Bits

Bit Name Description

2 CS (Channel Source) When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel

and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the

Data Memory and determine the source of the connection to the location's channel and stream.

1 CCO (CCO Bit) This bit is output on the CCO pin one channel early. The CCO bit for stream 0 is output first.

0 OE (Output Enable) If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output drive for the location's

channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing

switching matrices to be constructed. A 1 enables the driver and a 0 disables it.

76543210

No Corresponding Memory

- These bits give 0s if read Per Channel Control Bits

Bit Name Description

7-5

(1)

Stream Address Bits* The number expressed in binary notation on these 3 bits are the number of the stream for the source of the connection.

Bit 7 is the most significant bit, e.g., If bit 7 is 1, bit 6 is 0 and bit 5 is 0 then the source of the connection is a channel on

RX4.

4-0

(1)

Channel Address Bits* The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the

connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4

is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19.

76543210

Stream Address Bits Channel Address Bits

NOTE:

1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with

this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location.

P1-P3 P4-P6 P7-P9 P10-P11

IDT72V8980J8

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