LTC3520
19
3520fa
Most applications require a faster transient response than
can be attained using Type I compensation in order to reduce
the size of the output capacitor. To achieve a higher loop
bandwidth, Type III compensation is required, providing
two zeros to compensate for the double pole response of
the output fi lter. Referring to Figure 7, the location of the
compensation poles and zeros are given as follows:
f
RC
Hz Hz
f
RC
POLE
P
ZERO
ZP
1
1
1
1
1
2 32000 1
0
1
2
≅≅
=
π
π
()
HHz
f
RC
Hz
f
RC
Hz
ZERO
Z
POLE
ZP
2
1
2
2
1
21
1
2
=
=
π
π
where all resistances are in ohms and all capacitances
are in farads.
PCB Layout Considerations
The LTC3520 switches large currents at high frequencies.
Special care should be given to the PCB layout to ensure
stable, noise-free operation. Figure 8 depicts the recom-
mended PCB layout to be utilized for the LTC3520. A few
key guidelines follow:
1. All circulating current paths should be kept as short
as possible. This can be accomplished by keeping the
routes to all bold components in Figure 8 as short
and as wide as possible. Capacitor ground connec-
tions should via down to the ground plane by the
shortest route possible. The bypass capacitors on
PV
IN1
, PV
IN2
, and PV
IN3
should be placed as close
to the IC as possible and should have the shortest
possible paths to ground.
2. The small signal ground pad (SGND) should have a
single-point connection to the power ground. A con-
venient way to achieve this is to short the pin directly
to the Exposed Pad as shown in Figure 8.
3. The components shown in bold and their connections
should all be placed over a complete ground plane to
reduce the cross-sectional area of circulating current
paths.
4. To prevent large circulating currents from disrupting
the output voltage sensing, the ground for each resistor
divider should be returned directly to the small signal
ground pin (SGND).
5. Use of vias in the die attach pad will enhance the ther-
mal environment of the converter especially if the vias
extend to a ground plane region on the exposed bottom
surface of the PCB.
Figure 7. Type III Compensation Network
APPLICATIONS INFORMATION
0.782V
R1
R2
3520 F07
FB1
18
V
C1
C
Z1
V
OUT
15
C
P2
–
+
C
P1
R
Z
