S5U13771P00C100

X82A-C-001-01 1
Revision 1.02
GRAPHICS
S1D13771
S1D13771 TV-Out Graphics Engine August 2007
S1D13771 is an extremely low cost, low pin-count device providing direct support for TV output. A high quality
internal scaler and complex TV filters allow for VGA resolution input to be stored using a minimum amount of
memory, while still providing smoothly scaled output to the full resolution specified by either PAL or NTSC
standards. S1D13771 is the ideal solution for cellular phone markets where TV output is a requirement.
The minimal feature set and high level of integration (embedded SRAM and high output DAC) provides a low cost,
low power, single chip solution to meet the demands of embedded markets requiring TV output, such as Mobile
Communications devices.
FEATURES
SYSTEM BLOCK DIAGRAM
Embedded SRAM
Low Operating Voltage
Parallel Host Interface
High Output DAC
High Quality Scaler provides Bi-Cubic input/output
scaling
TV Connect/Disconnect Detection
PAL and NTSC output
Auto-Border / Auto-Center of TV Image with a pro-
grammable color
15-Tap Programmable Chrominance / Luminance Filters
3x3 Pixel Filter
Software Initiated Power Save Mode
Original Image
TV Display
(written to S1D13771)
640x480 Input
720x576
CPU
Direct TV output
13771
720x576
Input is processed by
the scaler and stored
in internal memory
Output is filtered,
or
processed by the scaler,
and output to TV
Output is filtered,
processed by the scaler,
automatically bordered,
and output to TV
640x480
Revision 1.02
X82A-C-001-01 2
GRAPHICS
S1D13771
DESCRIPTION
THEORY OF OPERATION
The S1D13771 contains an embedded SRAM frame buffer allowing up to VGA resolution to be stored using a high
quality scaling algorithm. All stored images can be scaled-up or scaled-down for display on the TV using bi-cubic
scaling. If the resulting image is not scaled-up to the maximum resolution defined by the TV standard, the image
is automatically centered and bordered with a programmable border color.
A 3x3 pixel filter and programmable chrominance / luminance filters are provided to generate a high quality TV
image.
Integrated Frame Buffer
Embedded SRAM
CPU Interface
8-bit Parallel Indirect Interface (Intel 80)
Chip select is used to select device. When in-active, any
input data/commands are ignored.
Input Formats
RGB: 8:8:8, 6:6:6, 5:6:5
YUV: 4:2:2
All input data is processed by the scaler and stored in
internal memory.
TV Output
Composite PAL / NTSC output
15-Tap Programmable Chrominance / Luminance Filters
Scaler uses Bi-Cubic scaling to scale-up or scale-down
Auto-Border / Auto-Center
Programmable border color
Square Pixel Correction
Macrovision Protection Support (bond-out option)
TV Connect/Disconnect Detection
Image Enhancement Engine
3x3 Pixel filter
User defined coefficients
Individual control for each YUV component
Display effects include: smooth, sharpen, blur, detail,
edge enhance, emboss, contour, flicker filter, sepia, and
dot crawl correction
Clock Input
Single digital clock input used for: (18-27MHz typical)
Internal PLL reference clock (PLL used for system clock)
TV Timing (can optionally use PLL÷2)
DDS Timing (can optionally use PLL÷2)
Miscellaneous
Power save mode
Software controllable via registers
General purpose IO pins
Configurable interrupt associated with GPIO inputs
CORE
VDD
1.5 Volts and IO
VDD
1.8 to 3.3 Volts
DAC power supply: 3.0 Volts
Package: W-CSP 64-pin (4.46 x 4.46mm)
CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS
S1D13771 Technical
Documentation
CPU Independent
Software Utilities
Evaluation Boards Royalty Free source level
driver code
© SEIKO EPSON CORPORATION 2006-2007. All rights reserved.
Information in this document is subject to change without notice. This is not an offer for sale. You may download and use this document, but only for your own use in evaluating Seiko
Epson/EPSON products. You may not modify the document. Epson Research and Development, Inc. disclaims any representation that the contents of this document are accurate or
current. The Programs/Technologies described in this document may contain material protected under U.S. and/or International Patent laws.
EPSON is a registered trademark of Seiko Epson Corporation. All other trademarks are the property of their respective owners.
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Fax: (408) 922-0238
http://www.eea.epson.com/

S5U13771P00C100

Mfr. #:
Manufacturer:
Epson ICs
Description:
Display Development Tools S1D13771 EVAL BRD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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