Data Sheet ADuM4154
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at T
A
= 25°C and V
DD1
= V
DD2
= 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ V
DD1
≤ 3.6 V, 3.0 V ≤ V
DD2
≤ 3.6 V, and −40°C ≤ T
A
≤ +125°C, unless otherwise noted.
Switching specifications are tested with C
L
= 15 pF and CMOS signal levels, unless otherwise noted.
Table 4. Switching Specifications
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
MCLK, MO, SO
SPI Clock Rate SPI
MCLK
1 12.5 MHz
Data Rate Fast (MO, SO) DR
FAS T
2 34 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
30 21 ns 50% input to 50% output
Pulse Width PW 100 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 2 ns |t
PLH
− t
PHL
|
Codirectional Channel Matching
1
t
PSKCD
3 2 ns
HS
MSS
Data Rate Fast DR
FAS T
2 34 Mbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
34 34 ns 50% input to 50% output
Pulse Width PW 100 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 3 ns |t
PLH
− t
PHL
|
Setup Time
2
MSS
SETUP
1.5 10 ns
Jitter, High Speed J
HS
1 1 ns
SSA0, SSA1
Data Rate Slow DR
SLOW
250 250 kbps Within PWD limit
Propagation Delay t
PHL
, t
PLH
0.1 2.6 0.1 2.6 µs 50% input to 50% output
Pulse Width PW 4 4 µs Within PWD limit
Jitter, Low Speed J
LS
2.5 2.5 µs
SSAx
3
Minimum Input Skew
4
t
SSAx SKEW
3
40 40 ns
1
Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the
isolation barrier.
2
The
MSS
signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that
MSS
reaches the
output ahead of another fast signal, set up
MSS
prior to the competing signal by different times depending on speed grade.
3
SSAx = SSA0 or SSA1.
4
An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end
application, the leading pulse must be at least 1 t
SSAx SKEW
ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. A | Page 5 of 22