6.42
IDT71256S/L
CMOS Static RAM 256K (32K x 8-Bit) Military, Commercial, and Industrial Temperature Ranges
5
AC Electrical Characteristics (VCC = 5.0V ± 10%, All Temperature Ranges)
Low VCC Data Retention Waveform
2946 drw 06
RETENTION
MODE
4.5V
4.5V
V
DR
≥ 2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
NOTES:
1. 0° to +70°C temperature range only.
2. This parameter is guaranteed by device characterization, but is not production tested.
3. –55°C to +125°C temperature range only.
Symbol Parameter
71256L20
(1)
71256S25
71256L25
71256S35
71256L35
71256S45
(3 )
71256L45
(3 )
Unit
Min. Max. Min. Max. Min. Max. Min. Max.
Read Cycle
t
RC
Read Cycle Time 20
____
25
____
35
____
45
____
ns
t
AA
Address Access Time
____
20
____
25
____
35
____
45 ns
t
ACS
Chip Select Access Time
____
20
____
25
____
35
____
45 ns
t
CL Z
(2 )
Chip Select to Output in Low-Z 5
____
5
____
5
____
5
____
ns
t
CHZ
(2)
Chip Deselect to Output in High-Z
____
10
____
11
____
15
____
20 ns
t
OE
Output Enable to Output Valid
____
10
____
11
____
15
____
20 ns
t
OLZ
(2)
Output Enable to Output in Low-Z 2
____
2
____
2
____
0
____
ns
t
OHZ
(2 )
Output Disable to Output in High-Z 2 8 2 10 2 15
____
20 ns
t
OH
Output Hold from Address Change 5
____
5
____
5
____
5
____
ns
Write Cycle
t
WC
Write Cycle Time 20
____
25
____
35
____
45
____
ns
t
CW
Chip Select to End-of-Write 15
____
20
____
30
____
40
____
ns
t
AW
Address Valid to End-of-Write 15
____
20
____
30
____
40
____
ns
t
AS
Address Set-up Time 0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width 15
____
20
____
30
____
35
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
0
____
ns
t
DW
Data to Write Time Overlap 11
____
13
____
15
____
20
____
ns
t
WHZ
(2)
Write Enable to Output in High-Z
____
10
____
11
____
15
____
20 ns
t
DH
Data Hold from Write Time 0
____
0
____
0
____
0
____
ns
t
OW
(2)
Output Active from End-of-Write 5
____
5
____
5
____
5
____
ns
2946 tbl 12
