MC74HC595ANG

© Semiconductor Components Industries, LLC, 2011
May, 2011 Rev. 13
1 Publication Order Number:
MC74HC595A/D
MC74HC595A
8-Bit Serial-Input/Serial or
Parallel-Output Shift
Register with Latched
3-State Outputs
HighPerformance SiliconGate CMOS
The MC74HC595A consists of an 8bit shift register and an 8bit
Dtype latch with threestate parallel outputs. The shift register
accepts serial data and provides a serial output. The shift register also
provides parallel data to the 8bit latch. The shift register and latch
have independent clock inputs. This device also has an asynchronous
reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on
CMOS MPUs and MCUs.
Features
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC
Standard No. 7 A
Chip Complexity: 328 FETs or 82 Equivalent Gates
Improvements over HC595
Improved Propagation Delays
50% Lower Quiescent Power
Improved Input Noise and Latchup Immunity
These Devices are PbFree, Halogen Free and are RoHS Compliant
http://onsemi.com
MARKING
DIAGRAMS
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
G, G = PbFree Package
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
SOIC16
D SUFFIX
CASE 751B
TSSOP16
DT SUFFIX
CASE 948F
1
16
PDIP16
N SUFFIX
CASE 648
1
16
1
16
1
16
MC74HC595AN
AWLYYWWG
1
16
HC595AG
AWLYWW
HC
595A
ALYWG
G
1
16
(Note: Microdot may be in either location)
MC74HC595A
http://onsemi.com
2
LOGIC DIAGRAM
SERIAL
DATA
INPUT
14
11
10
12
13
SHIFT
CLOCK
RESET
LATCH
CLOCK
OUTPUT
ENABLE
SHIFT
REGISTER
LATCH
15
1
2
3
4
5
6
7
9
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
SQ
H
A
V
CC
= PIN 16
GND = PIN 8
PARALLEL
DATA
OUTPUTS
SERIAL
DATA
OUTPUT
PIN ASSIGNMENT
13
14
15
16
9
10
11
125
4
3
2
1
8
7
6
LATCH CLOCK
OUTPUT ENABLE
A
Q
A
V
CC
SQ
H
RESET
SHIFT CLOCK
Q
E
Q
D
Q
C
Q
B
GND
Q
H
Q
G
Q
F
ORDERING INFORMATION
Device Package Shipping
MC74HC595ANG PDIP16
(PbFree)
500 Units / Rail
MC74HC595ADG SOIC16
(PbFree)
48 Units / Rail
MC74HC595ADR2G SOIC16
(PbFree)
2500 Tape & Reel
MC74HC595ADTR2G TSSOP16*
(PbFree)
2500 Tape & Reel
MC74HC595AFELG SOEIAJ16
(PbFree)
2000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently PbFree.
MC74HC595A
http://onsemi.com
3
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) –0.5 to +7.0 V
V
in
DC Input Voltage (Referenced to GND) –0.5 to V
CC
+0.5 V
V
out
DC Output Voltage (Referenced to GND) –0.5 to V
CC
+0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±35 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±75 mA
P
D
Power Dissipation in Still Air, Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
mW
T
stg
Storage Temperature –65 to +150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP, SOIC or TSSOP Package)
260
_C
V
ESD
ESD Withstand Voltage Human Body Model (Note 1)
Machine Model (Note 2)
Charged Device Model (Note 3)
>3000
>400
N/A
V
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
1. Tested to EIA/JESD22A114A.
2. Tested to EIA/JESD22A115A.
3. Tested to JESD22C101A.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage
(Referenced to GND)
0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol
Parameter Test Conditions
V
CC
V
Guaranteed Limit
Unit
– 55 to 25_C v 85_C v 125_C
V
IH
Minimum HighLevel Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum LowLevel Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum HighLevel Output
Voltage, Q
A
Q
H
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 6.0 mA
|I
out
| v 7.8 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.

MC74HC595ANG

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Counter Shift Registers 8-Bit 3 State Shift
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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