SPL505YC256BT Datasheet SPL505YC256BTT, SPL505YC256BT | P7-P9

SPL505YC25

......................Document #: 001-03543 Rev *E Page 7 of 27

2 1 PCI2_OE Output enable for PCI2, 0 = Output Disabled, 1 = Output Enabled

1 1 PCI1_OE Output enable for PCI1, 0 = Output Disabled, 1 = Output Enabled

0 1 PCI0_OE Output enable for PCI0, 0 = Output Disabled, 1 = Output Enabled

Byte 2: Control Register 2 (continued)

Bit @Pup Name Description

Byte 3: Control Register 3

Bit @Pup Name Description

7 1 SRC11_OE Output enable for SRC11, 0 = Output Disabled, 1 = Output Enabled

6 1 SRC10_OE Output enable for SRC10, 0 = Output Disabled, 1 = Output Enabled

5 1 SRC9_OE Output enable for SRC9, 0 = Output Disabled, 1 = Output Enabled

4 1 SRC8/ITP_OE Output enable for SRC8 or ITP, 0 = Output Disabled, 1 = Output Enabled

3 1 SRC7_OE Output enable for SRC7, 0 = Output Disabled, 1 = Output Enabled

2 1 SRC6_OE Output enable for SRC6, 0 = Output Disabled, 1 = Output Enabled

1 1 SRC5_OE Output enable for SRC5, 0 = Output Disabled, 1 = Output Enabled

0 1 SRC4_OE Output enable for SRC4, 0 = Output Disabled, 1 = Output Enabled

Byte 4: Control Register 4

Bit @Pup Name Description

7 1 SRC3_OE Output enable for SRC3, 0 = Output Disabled, 1 = Output Enabled

6 1 SRC2/SATA_OE Output enable for SATA/SRC2, 0 = Output Disabled, 1 = Output Enabled

5 1 SRC1_OE Output enable for SRC, 0 = Output Disabled, 1 = Output Enabled

4 1 SRC0/DOT96_OE Output enable for SRC0/DOT96

0 = Output Disabled, 1 = Output Enabled

3 1 CPU1_OE Output enable for CPU1, 0 = Output Disabled, 1 = Output Enabled

2 1 CPU0_OE Output enable for CPU0, 0 = Output Disabled, 1 = Output Enabled

1 1 PLL1_SS_EN Enable PLL1’s spread modulation,

0 = Spread Disabled 1 = Spread Enabled

0 1 PLL3_SS_EN Enable PLL3’s spread modulation

0 = Spread Disabled, 1 = Spread Enabled

Byte 5: Control Register 5

Bit @Pup Name Description

7 0 OE#_0/2_EN_A Enable OE#_0/2 (clk req)

0 = Disabled OE#_0/2, 1 = Enabled OE#_0/2,

6 0 OE#_0/2_SEL_A Set OE#_0/2  SRC0 or SRC2

0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2

5 0 OE#_1/4_EN_A Enable OE#_1/4 (clk req)

0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,

4 0 OE#_1/4_SEL_A Set OE#_1/4  SRC1 or SRC4

0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4

3 0 OE#_0/2_EN_B Enable OE#_0/2 (clk req)

0 = Disabled OE#_0/2 1 = Enabled OE#_0/2

2 0 OE#_0/2_SEL_B Set OE#_0/2  SRC0 or SRC2

0 = OE#_0/2SRC0, 1 = OE#_0/2SRC2

1 0 OE#_1/4_EN_B Enable OE#_1/4 (clk req)

0 = Disabled OE#_1/4, 1 = Enabled OE#_1/4,

0 0 OE#_1/4_SEL_B Set OE#_1/4 SRC1 or SRC4

0 = OE#_1/4SRC1, 1 = OE#_1/4SRC4

SPL505YC25

......................Document #: 001-03543 Rev *E Page 8 of 27

Byte 6: Control Register 6

Bit @Pup Name Description

7 0 OE#_6_EN Enable OE#_6 (clk req)  SRC6

6 0 OE#_8_EN Enable OE#_8 (clk req)  SRC8

5 0 OE#_9_EN Enable OE#_9 (clk req) SRC9

4 0 OE#_10_EN Enable OE#_10 (clk req)  SRC10

3 0 RESERVED RESERVED

2 0 RESERVED RESERVED

1 0 LCD_100_STP_CTRL Allows control of LCD_100 with assertion of PCI_STOP#

0 = Free runningLCD_100, 1 = Stopped with PCI_STOP#

0 0 SRC_STP_CTRL Allows control of SRC with assertion of PCI_STOP#

0 = Free running SRC 1 = Stopped with PCI_STOP#

Byte 7: Vendor ID

Bit @Pup Name Description

7 0 Rev Code Bit 3 Revision Code Bit 3

6 0 Rev Code Bit 2 Revision Code Bit 2

5 0 Rev Code Bit 1 Revision Code Bit 1

4 1 Rev Code Bit 0 Revision Code Bit 0

3 1 Vendor ID bit 3 Vendor ID Bit 3

2 0 Vendor ID bit 2 Vendor ID Bit 2

1 0 Vendor ID bit 1 Vendor ID Bit 1

0 0 Vendor ID bit 0 Vendor ID Bit 0

Byte 8: Control Register 8

Bit @Pup Name Description

7 0 Device_ID3 0000 = CK505 Yellow Cover Device, 56-pin TSSOP

0001 = CK505 Yellow Cover Device, 64-pin TSSOP

0010 = CK505 Yellow Cover Device, 48-pin QFN (reserved)

0011 = CK505 Yellow Cover Device, 56-pin QFN (reserved)

0100 = CK505 Yellow Cover Device, 64-pin QFN (reserved)

0101 = CK505 Yellow Cover Device, 72-pin QFN (reserved)

0110 = CK505 Yellow Cover Device, 48-pin SSOP (reserved)

0111 = CK505 Yellow Cover Device, 56-pin SSOP (reserved)

1000 = Reserved

1001 = Reserved

1010 = Reserved

1011 = Reserved

1100 = Reserved

1101 = Reserved

1110 = Reserved

1111 = Reserved

7 0 Device_ID2

5 0 Device_ID1

4 0 Device_ID0

3 0 RESERVED RESERVED

2 0 RESERVED RESERVED

1 0 SE1_OE SE1 Output enable 0 = Output Disabled, 1 = Output Enabled

0 0 SE2_OE SE2 Output enable 0 = Output Disabled, 1 = Output Enabled

Byte 9 Control Register 9

Bit @Pup Name Description

SPL505YC25

......................Document #: 001-03543 Rev *E Page 9 of 27

7 0 PCIF0_STP_CTRL Allows control of PCIF0 with assertion of PCI_STOP#

0 = Free running PCIF, 1 = Stopped with PCI_STOP#

6 HW_Pin TME_STRAP Trusted mode enable strap status, 0 = normal, 1 = no overclocking

5 1 REF_DSC1 REF drive strength control, See Byte 18 for more setting

0 = Low, 1 = High

4 0 TEST_MODE_SEL Mode select either REF/N or tri-state

0 = All output tri-state, 1 = All output REF/N

3 0 TEST_MODE_ENTRY Allow entry into test mode

0=Normal operation, 1=Enter test mode

2 1 IO_VOUT2 IO_VOUT[2,1,0]

000 = 0.3V

001 = 0.4V

010 = 0.5V

011 = 0.6V

100 = 0.7V

101 = 0.8V, Default

110 = 0.9V

111 = 1.0V

10 IO_VOUT1

01 IO_VOUT0

Byte 9 Control Register 9

Byte 10 Control Register 10

Bit @Pup Name Description

7 HW SRC5_EN_STRAP Read only bit for SRC5_EN_STRAP

0 = CPU/PCI_STOP enabled, 1 = SRC5 pair enabled

6 1 PLL3_EN PLL3 Enabled

0 = PLL3 disabled, 1 = PLL3 enabled

5 1 PLL2_EN PLL2 Enabled

0 = PLL2 disabled, 1 = PLL2 enabled

4 1 SRC_DIV_EN SRC Divider Enabled

0 = SRC Divider disabled, 1 = SRC Divider enabled

3 1 PCI_DIV_EN PCI Divider Enabled

0 = PCI Divider disabled, 1 = PCI Divider enabled

2 1 CPU_DIV_EN CPU Divider Enabled

0 = CPU Divider disabled, 1 = CPU Divider enabled

1 1 CPU1_STP_CRTL Allow control of CPU1 with assertion of CPU_STOP#

0 = Free running, 1 = Stopped with CPU_STOP#

0 1 CPU0_STP_CRTL Allow control of CPU0 with assertion of CPU_STOP#

0 = Free running, 1 = Stopped with CPU_STOP#

Byte 11 Control Register 11

Bit @Pup Name Description

7 HW PCI3_CFG1

6 HW PCI3_CFG0

5 0 25MHz_EN_SE1 25MHz Output Enabled applies to Powerdown / M1

(Only applies when PCI3/CGFG0 strap is set high to enter HW mode 3)

0 = 25MHz disabled in Powerdown / M1

1 = 25MHz enabled in Powerdown / M1; Sticky 1

4 1 RESERVED RESERVED

Output SSC Output SSC Output SSC

0 0 0 -Def CPU / SRC / PCI33 Down USB NA -- --

0 1 1 CPU Down USB NA SRC/PCI33 Down

1 0 2 CPU Center USB NA SRC/PCI33 Down

1 1 3 CPU Center USB/25M NA SRC/PCI33 Down

PLL2 PLL3

PCI3/

CGF1

PCI3/

CGF0 Mode

PLL1

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27

SPL505YC256BT

Mfr. #:

Buy SPL505YC256BT

Manufacturer:

Silicon Labs

Description:

IC CLOCK CK505 BEARLAKE 56TSSOP

Lifecycle:

New from this manufacturer.

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SPL505YC256BT

SPL505YC256BT

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