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70V27L20PF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Commercial and Industrial Temperature Range
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
13
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = V
IH)".
2. To ensure that the earlier of the two ports wins.
3. t
BDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(6)
70V27X15
Com'l Only
70V27X20
Com'l & Ind
70V27X25
Com'l Only
UnitSymbol Parameter Min.Max.Min.Max.Min.Max.
BUSY TIMING (M/S=V
IH
)
t
BAA
BUSY Access Time from Address Match
____
15
____
20
____
25 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
15
____
20
____
25 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
15
____
20
____
25 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
15
____
20
____
25 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
17
____
35
____
35 ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
20
____
ns
BUSY TIMING (M/S=V
IL
)
t
WB
BUSY Input to Write
(4)
0
____
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
12
____
15
____
20
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
30
____
45
____
55 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
25
____
30
____
50 ns
3603 tbl 14a
70V27X35
Com'l & Ind
70V27X55
Com'l Only
UnitSymbol Parameter Min. Max. Min. Max.
BUSY TIMING (M/S =V
IH
)
t
BAA
BUSY Access Time from Address Match
____
35
____
45 ns
t
BDA
BUSY Disable Time from Address Not Matched
____
35
____
45 ns
t
BAC
BUSY Access Time from Chip Enable Low
____
35
____
45 ns
t
BDC
BUSY Disable Time from Chip Enable High
____
35
____
45 ns
t
APS
Arbitration Priority Set-up Time
(2)
5
____
5
____
ns
t
BDD
BUSY Disable to Valid Data
(3)
____
40
____
50 ns
t
WH
Write Hold After BUSY
(5)
25
____
25
____
ns
BUSY TIMING (M/S =V
IL
)
t
WB
BUSY Input to Write
(4)
0
____
0
____
ns
t
WH
Write Hold After BUSY
(5)
25
____
25
____
ns
PORT-TO-PORT DELAY TIMING
t
WDD
Write Pulse to Data Delay
(1)
____
65
____
85 ns
t
DDD
Write Data Valid to Read Data Delay
(1)
____
60
____
80 ns
3603 tbl 14b
Commercial and Industrial Temperature Range
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
14
Timing Waveform of Write with Port-to-Port Read and BUSY
(2,5)
(M/S = VIH)
(4)
NOTES:
1. t
WH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W
"B", until BUSY"B" goes HIGH.
3. t
WB is only for the "Slave" version.
Timing Waveform Write with BUSY (M/S = VIL)
3603 drw 11
t
DW
t
APS
ADDR
"A"
t
WC
DATA
OUT "B"
MATCH
t
WP
R/W
"A"
DATA
IN "A"
ADDR
"B"
t
DH
VALID
(1)
MATCH
BUSY
"B"
t
BDA
VALID
t
BDD
t
DDD
(3)
t
WDD
t
BAA
NOTES:
1. To ensure that the earlier of the two ports wins. t
APS is ignored for M/S = VIL (SLAVE).
2. CE
L = CER = VIL (refer to Chip Enable Truth Table).
3. OE = V
IL for the reading port.
4. If M/S = V
IL (SLAVE), then BUSY is an input. Then for this example BUSY "A"= VIH and BUSY "B"= input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
3603 drw 12
R/W
"A"
BUSY
"B"
t
WP
t
WB
R/W
"B"
t
WH
(2)
(3)
(1)
,
,
Commercial and Industrial Temperature Range
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
15
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing
(M/S = VIH)
(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If t
APS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
3. Refer to Chip Enable Truth Table.
Waveform of BUSY Arbitration Controlled by CE
Timing
(M/S = VIH)
(1,3)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1)
3603 drw 13
ADDR
"A"
and
"B"
ADDRESSES MATCH
CE
"B"
BUSY
"B"
t
APS
t
BAC
t
BDC
(2)
CE
"A"
3603 drw 14
ADDR
"A"
ADDRESS "N"
ADDR
"B"
BUSY
"B"
t
APS
t
BAA
t
BDA
(2)
MATCHING ADDRESS "N"
Symbol Parameter
70V27X15
Com'l Only
70V27X20
Com'l & Ind
70V27X25
Com'l Only
UnitMin. Max. Min. Max. Min. Max.
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
____
0
____
ns
t
WR
Write Recovery Time 0
____
0
____
0
____
ns
t
INS
Inte rrup t Set Time
____
15
____
20
____
25 ns
t
INR
Inte rrup t Re s e t Time
____
25
____
20
____
35 ns
3603 tbl 15a
Symbol Parameter
70V27X35
Com'l & Ind
70V27X55
Com'l Only
UnitMin. Max. Min. Max.
INTERRUPT TIMING
t
AS
Address Set-up Time 0
____
0
___ _
ns
t
WR
Write Recovery Time 0
____
0
___ _
ns
t
INS
Interrup t Set Time
____
30
____
40 ns
t
INR
Interrup t Reset Time
____
35
____
45 ns
3603 tbl 15b
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

70V27L20PF

Mfr. #:
Buy 70V27L20PF
Manufacturer:
IDT
Description:
SRAM 32Kx16 3.3V DUAL- PORT RAM
Lifecycle:
New from this manufacturer.
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