MC33470
http://onsemi.com
10
APPLICATIONS INFORMATION
Design Example
Given the following requirements, design a switching
dc−to−dc converter:
= 5.0 V
= 12 V
= 10111 − Output Voltage = 2.8 V
= 0.3 A to 14 A
V
CC
V
CCP
VID4−0
bits
Output
current
Efficiency > 80% at full load
Output ripple voltage ≈ 1% of output voltage
1. Choose power MOSFETs.
In order to meet the efficiency requirement, MOSFETs
should be chosen which have a low value of R
DS(on)
. However,
the threshold voltage rating of the MOSFET must also be
greater than 1.5 V, to prevent turn on of the synchronous
rectifier MOSFETs due to dv/dt coupling through the Miller
capacitance of the MOSFET drain−to−source junction.
Figure 17 shows the gate voltage transient due to this effect.
In this design, choose two parallel MMSF3300 MOSFETs
for both the main switch and the synchronous rectifier to
maximize efficiency.
2. D ≈ V
O
/V
in
= 2.8/5.0 = 0.56
3. Inductor selection
In order to maintain continuous mode operation at 10% of
full load current, the minimum value of the inductor will be:
L
min
= (V
in
− V
O
)(DTs)/(2I
O
min
)
= (5 − 2.8)(0.56 x 3.3 ms)/(2 x 1.4 A) = 1.45 mH
Coilcraft’s U6904, or an equivalent, provides a surface
mount 1.5 mH choke which is rated for for full load current.
4. Output capacitor selection
V
ripple
≈ D I
L
x ESR, where ESR is the equivalent series
resistance of the output capacitance. Therefore:
ESR
max
= V
ripple
/D I
L
= 0.01 x 2.8 V/1.4 A = 0.02 W
maximum
The AVX TPS series of tantalum chip capacitors may be
chosen. Or OSCON capacitors may be used if leaded parts are
acceptable. In this case, the output capacitance consists of two
parallel 820 mF, 4.0 V capacitors. Each capacitor has a
maximum specified ESR of 0.012 W.
5. Input Filter
As with all buck converters, input current is drawn in pulses.
In this case, the current pulses may be 14 A peak. If a 1.5 mH
choke is used, two parallel OSCON 150 mF, 16 V capacitors
will provide a filter cutoff frequency of 7.5 kHz.
6. Feedback Loop Compensation
The corner frequency of the output filter with L = 1.5 mH and
C
o
= 1640 mF is 3.2 kHz. In addition, the ESR of each output
capacitor creates a zero at:
f
z
= 1/(2π C ESR) = 1/(2π x 820 mF x 0.012) = 16.2 kHz
The dc gain of the PWM is: Gain = V
in
/V
pp
= 5/1 = 5.0.
Where V
pp
is the peak−to−peak sawtooth voltage across the
internal timing capacitor. In order to make the feedback loop
as responsive as possible to load changes, choose the unity
gain frequency to be 10% of the switching frequency, or
30 kHz. Plotting the PWM gain over frequency, at a frequency
of 30 kHz the gain is about −16.5 dB = 0.15. Therefore, to have
a 30 kHz unity gain loop, the error amplifier gain at 30 kHz
should be 1/0.15 = 6.7. Choose a design phase margin for the
loop of 60°. Also, choose the error amp type to be an integrator
for best dc regulation performance. The phase boost needed by
the error amplifier is then 60° for the desired phase margin.
Then, the following calculations can be made:
k = tan [Boost/2 + 45°] = tan [60/2 + 45] = 3.73
Error Amp zero freq = f
c
/K = 30 kHz/3.73 = 8.0 kHz
Error Amp pole freq = K
fc
= 3.73 x 30 kHz = 112 kHz
R2 = Error Amp Gain/G
m
= 6.7/800 m = 8.375 k − use an
8.2 k standard value
C16 = 1/(2π R2 f
z
) = 1/(2π x 8.2 k x 8.0 kHz)
= 2426 pF − use 2200 pF
C17 = 1/(2π R2 f
p
) = 1/(2π x 8.2 k x 112 kHz)
= 173 pF − use 100 pF
The complete design is shown in Figure 14. The PC board
top and bottom views are shown in Figures 18 and 19.
Figure 17. Voltage Coupling Through Miller
Capacitance
