14
AT89C4051
1001D–06/01
Shift Register Mode Timing Waveforms
AC Testing Input/Output Waveforms
(1)
Note: 1. AC Inputs during testing are driven at V
CC
- 0.5V for a logic 1 and 0.45V for a logic 0. Timing measurements are made at V
IH
min. for a logic 1 and V
IL
max. for a logic 0.
Float Waveforms
(1)
Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to
float when 100 mV change frothe loaded V
OH
/V
OL
level occurs.
Serial Port Timing: Shift Register Mode Test Conditions
V
CC
= 5.0V ± 20%; Load Capacitance = 80 pF
Symbol Parameter
12 MHz Osc Variable Oscillator
UnitsMin Max Min Max
t
XLXL
Serial Port Clock Cycle Time 1.0 12t
CLCL
µs
t
QVXH
Output Data Setup to Clock Rising Edge 700 10t
CLCL
-133 ns
t
XHQX
Output Data Hold after Clock Rising Edge 50 2t
CLCL
-117 ns
t
XHDX
Input Data Hold after Clock Rising Edge 0 0 ns
t
XHDV
Clock Rising Edge to Input Data Valid 700 10t
CLCL
-133 ns
