PB002000-TVC1099
ZiLOG W
ORLDWIDE
H
EADQUARTERS
• 910 E. H
AMILTON
A
VENUE
• C
AMPBELL
, CA 95008
T
ELEPHONE
: 408.558.8500 •
CSUPPORT
@
ZILOG
.
COM
•
WWW
.
ZILOG
.
COM
Z90365
and
Z90361
32
KWord Television Controller
with On-Screen Display
Product Block Diagram
General Description
The Z90365 and Z90361 are members of ZiLOG’s Digital
Signal Processor (DSP)-based TV controller family. They
provide advanced On-Screen Display (OSD), Closed
Caption and TV control features on a single chip. The
Z90365 and Z90361 are the ROM and OTP versions
respectively with 32KWords of ROM and programmable
memory. Both have 640 words of RAM.
The single-cycle, DSP provides high processing power. It
allows the Z90365 and Z90361 to support high character
resolution, expanded color palette selections, expanded
character accommodation, multiple character size choices
and flexible, software-controlled character attributes. The
Z90365 is an ideal choice for mid-to-high end TV products
for both PAL and NTSC standards.
The Z9036x family consists of three basic devices:
•
The Z90365 masked ROM
•
The Z90361 One-Time-Programmable device
•
The Z90369 In-Circuit Emulation (ICE) chip
In addition, ZiLOG provides a complete development suite
for TV product development, which includes emulator,
evaluation kit, C-Compiler, Application Programmer
Interface (API), Zilog Developer Studio (ZDS) software,
and font editor. These tools help TV developers work
efficiently and effectively with quick time to market.
On-Screen Display Features
•
14 rows x 32 columns screen display
•
16x16, 16x18, and 16x20 pixel matrices
•
2X and 3X character stretch with smoothing
•
512-characters with configurable display attributes on
character by character basis including:
-
Underlining / Italic / Blinking
-
Eight foreground and background colors
-
Character position offset delay
-
Background transparency
•
65 color palettes
TV Control Features
•
Five Channel, 4-bit Analog-to-Digital Converter
(ADC) which supports:
-
Automatic frequency tuning (AFT)
-
Analog keypad entry
-
Audio level input adjustment
-
Video Blanking Interval (VBI) decoding
•
Seven Pulse Width Modulators (PWM) to control
video, audio and external Voltage Synthesis Tuner
(VST)
•
Master/Slave I
2
C bus interface.
•
Twenty programmable I/Os
•
On-chip Horizontal Synchronization (H
SYNC
) and
Vertical Synchronization (V
SYNC
) generation circuits
•
On-chip Infrared (IR) capture register
Controller Features
•
16-bit Single-cycle instruction execution
•
Phase Lock Loop (PLL), controlled by a 32KHz
external crystal
•
32KWord ROM or OTP with flexible Character
Generation ROM
•
640 Words of RAM
•
42-pin SDIP package
32K Words ROM or OTP
DSP Core RAM
ADC
OSD
PWM I
2
C I/O Ports
