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9FGV0631CKLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
JUNE 23, 2017 7 6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
9FGV0631C DATASHEET
Electrical Characteristics–DIF Low Power HCSL Outputs
Electrical Characteristics–Filtered Phase Jitter Parameters - PCIe Common Clocked
(CC) Architectures
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
Scope avera
g
in
g
on fast settin
g
1.8 2.7 4.4
V/ns
1,2,3
Scope averaging on slow setting 1.4 2.1 3.4
V/ns
1,2,3
Slew rate matchin
g
Δ
Trf Slew rate matchin
g
, Scope avera
g
in
g
on 4 20
%
1,2,4
Voltage High V
HIGH
660 793 850 7
Voltage Low V
LOW
-150 16 150 7
Max Voltage Vmax 831 1150 7
Min Volta
g
e Vmin -300 -95 7
Vswin
g
Vswin
g
Scope avera
g
in
g
off 300 1555 mV 1,2,7
Crossing Voltage (abs) Vcross_abs Scope averaging off 250 429 550 mV 1,5,7
Crossing Voltage (var)
Δ
-Vcross Scope averaging off 12 140 mV 1,6,7
2
Measured from differential waveform
7
At default SMBus amplitude settin
g
s.
1
Guaranteed by design and characterization, not 100% tested in production.
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6
The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Slew rate Trf
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
mV
Measurement on single ended signal using
absolute value. (Scope avera
g
in
g
off)
mV
T
AMB
= over the specified operating range. Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
SYMBOL PARAMETER CONDITIONS MIN TYP MAX
Specification
Limit
UNITS NOTES
t
jphPCIeG1-CC
PCIe Gen 1 21 25 35 86 ps (p-p) 1, 2, 3
PCIe Gen 2 Low Band
10kHz < f < 1.5MHz
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
0.9 0.9 1.1 3
ps
(rms)
1, 2
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
(PLL BW of 5-16MHz, 8-16MHz, CDR = 5MHz)
1.5 1.6 1.9 3.1
ps
(rms)
1, 2
t
jphPCIeG3-CC
PCIe Gen 3
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
0.3 0.37 0.44 1
ps
(rms)
1, 2
t
jphPCIeG4-CC
PCIe Gen 4
(PLL BW of 2-4MHz, 2-5MHz, CDR = 10MHz)
0.3 0.37 0.44 0.5
ps
(rms)
1, 2
Notes on PCIe Filtered Phase Jitter Table
1
Applies to all differential outputs, guaranteed by design and characterization.
Phase Jitter,
PLL Mode
t
jphPCIeG2-CC
2
Calculated from Intel-supplied Clock Jitter Tool, with spread on and off.
3
Sample size of at least 100K cycles. This figure extrapolates to 108ps pk-pk at 1M cycles for a BER of 1
-12
.
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR 8 JUNE 23, 2017
9FGV0631C DATASHEET
Electrical Characteristics–REF
Clock Periods–Differential Outputs with Spread Spectrum Disabled
Clock Periods–Differential Outputs with Spread Spectrum Enabled
Clock Periods–Single-ended Outputs
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER SYMBO
L
CONDITIONS MIN TYP MAX UNITS Notes
Long Accuracy ppm see Tperiod min-max values ppm 1,2
Clock period T
p
eriod
25 MHz output 40 ns 2
Rise/Fall Slew Rate t
rf1
Byte 3 = 1F, 20% to 80% of VDDREF 0.6 1 1.6 V/ns 1
Rise/Fall Slew Rate t
rf1
Byte 3 = 5F, 20% to 80% of VDDREF 0.9 1.4 2.2 V/ns 1,3
Rise/Fall Slew Rate t
rf1
Byte 3 = 9F, 20% to 80% of VDDREF 1.1 1.7 2.7 V/ns 1
Rise/Fall Slew Rate t
rf1
Byte 3 = DF, 20% to 80% of VDDREF 1.1 1.8 2.9 V/ns 1
Duty Cycle d
t1X
V
T
= VDD/2 V 45 49.1 55 % 1,4
Duty Cycle Distortion d
tcd
V
T
= VDD/2 V 0 2 4 % 1,5
Jitter, cycle to cycle t
j
c
y
c-c
y
c
V
T
= VDD/2 V 19.1 250 ps 1,4
Noise floor t
j
dBc1k
1kHz offset -129.8 -105 dBc 1,4
Noise floor t
j
dBc10k
10kHz offset to Nyquist -143.6 -115 dBc 1,4
Jitter, phase t
jphREF
12kHz to 5MHz 0.63 1.5
ps
(rms)
1,4
1
Guaranteed by design and characterization, not 100% tested in production.
3
Default SMBus Value
4
When driven by a crystal.
5
When driven by an external oscillator via the X1 pin, X2 should be floating.
2
All Lon
g
Term Accuracy and Clock Period specifications are
g
uaranteed assumin
g
that REF is trimmed to 25.00 MHz
0
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 100.00 9.94900 9.99900 10.00000 10.00100 10.05100 ns 1,2
Measurement Window
UnitsSSC OFF
Center
Freq.
MHz
Notes
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Ma
x
+SSC
Short-Term
Average
Ma
x
+c2c jitter
AbsPer
Max
DIF 99.75 9.94906 9.99906 10.02406 10.02506 10.02607 10.05107 10.10107 ns 1,2
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy specifications are guaranteed with the assumption that the crystal input is tuned to exactly 14.31818MHz.
Measurement Window
UnitsSSC ON
Center
Freq.
MHz
Notes
1 Clock 1us 0.1s 0.1s 0.1s 1us 1 Clock
-c2c jitter
AbsPer
Min
-SSC
Short-Term
Average
Min
- ppm
Long-Term
Average
Min
0 ppm
Period
Nominal
+ ppm
Long-Term
Average
Max
+SSC
Short-Term
Average
Max
+c2c jitter
AbsPer
Max
REF 25.000 39.79880 39.99880 40.00000 40.00120 40.20120 ns 1,2
NotesSSC OFF
Center
Freq.
MHz
Measurement Window
Units
JUNE 23, 2017 9 6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
9FGV0631C DATASHEET
General SMBus Serial Interface Information
How to Write
• Controller (host) sends a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) sends the byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through Byte
N+X-1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a stop bit
Note: Read/Write address is latched on SADR pin.
How to Read
• Controller (host) will send a start bit
• Controller (host) sends the write address
• IDT clock will acknowledge
• Controller (host) sends the beginning byte location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit
• Controller (host) sends the read address
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N+X-1
• IDT clock sends Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
• Controller (host) will need to acknowledge each byte
• Controller (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X Byte
ACK
O
OO
OO
O
Byte N + X - 1
ACK
PstoP bit
Index Block Read Operation
Controller (Host) IDT (Slave/Receiver)
TstarT bit
Slave Address
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address
RD ReaD
ACK
Data Byte Count=X
ACK
X Byte
Beginning Byte N
ACK
O
OO
OO
O
Byte N + X - 1
N Not acknowledge
PstoP bit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

9FGV0631CKLF

Mfr. #:
Buy 9FGV0631CKLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 6 Output 1.8V PCIe 1-2-3 Clock Gen
Lifecycle:
New from this manufacturer.
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