IRFH5207TRPBF

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IRFH5207PbF
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case (Bottom)
Fig 8. Maximum Safe Operating Area
Fig 9. Maximum Drain Current Vs.
Case (Bottom) Temperature
Fig 7. Typical Source-Drain Diode Forward Voltage
Fig 10. Threshold Voltage Vs. Temperature
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
V
SD
, Source-to-Drain Voltage (V)
1.0
10
100
1000
I
S
D
,
R
e
v
e
r
s
e
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
T
J
= 25°C
T
J
= 150°C
V
GS
= 0V
25 50 75 100 125 150
T
C
, Case Temperature (°C)
0
15
30
45
60
75
I
D
,
D
r
a
i
n
C
u
r
r
e
n
t
(
A
)
1E-006 1E-005 0.0001 0.001 0.01 0.1
t
1
, Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
10
T
h
e
r
m
a
l
R
e
s
p
o
n
s
e
(
Z
t
h
J
C
)
°
C
/
W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
-75 -50 -25 0 25 50 75 100 125 150
T
J
, Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
V
G
S
(
t
h
)
,
G
a
t
e
t
h
r
e
s
h
o
l
d
V
o
l
t
a
g
e
(
V
)
I
D
= 1.0A
ID = 1.0mA
ID = 150μA
ID = 100μA
0.10 1 10 100
V
DS
, Drain-to-Source Voltage (V)
0.1
1
10
100
1000
I
D
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
C
u
r
r
e
n
t
(
A
)
OPERATION IN THIS AREA
LIMITED BY RDS(on)
Tc = 25°C
Tj = 150°C
Single Pulse
100μsec
1msec
10msec
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IRFH5207PbF
Fig 13. Maximum Avalanche Energy vs. Drain Current
Fig 12. On-Resistance vs. Gate Voltage
Fig 14b. Unclamped Inductive Waveforms
Fig 14a. Unclamped Inductive Test Circuit
t
p
V
(BR)DSS
I
AS
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
V
DS
+
-
V
DD
DRIVER
A
15V
20V
Fig 15a. Switching Time Test Circuit
Fig 15b. Switching Time Waveforms
V
GS
V
DS
90%
10%
t
d(on)
t
d(off)
t
r
t
f
V
DS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1
R
D
V
GS
R
G
D.U.T.
10V
+
-
V
DD
V
GS
4 6 8 10 12 14 16 18 20
V
GS,
Gate -to -Source Voltage (V)
5
10
15
20
25
R
D
S
(
o
n
)
,
D
r
a
i
n
-
t
o
-
S
o
u
r
c
e
O
n
R
e
s
i
s
t
a
n
c
e
(
m
Ω
)
I
D
= 43A
T
J
= 25°C
T
J
= 125°C
25 50 75 100 125 150
Starting T
J
, Junction Temperature (°C)
0
50
100
150
200
250
300
350
400
E
A
S
,
S
i
n
g
l
e
P
u
l
s
e
A
v
a
l
a
n
c
h
e
E
n
e
r
g
y
(
m
J
)
I
D
TOP 4.4A
11A
BOTTOM 43A
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IRFH5207PbF
Fig 16. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET
®
Power MOSFETs
Fig 17. Gate Charge Test Circuit
Fig 18. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2 Qgd Qgodr
Circuit Layout Considerations
Low Stray Inductance
Ground Plane
Low Leakage Inductance
Current Transformer
P.W.
Period
di/dt
Diode Recovery
dv/dt
Ripple 5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D =
P. W .
Period
* V
GS
= 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
R
G
V
DD
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
D.U.T
1K
VCC
DUT
0
L
S

IRFH5207TRPBF

Mfr. #:
Manufacturer:
Infineon Technologies
Description:
MOSFET N-CH 75V 13A 8-PQFN
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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