Detailed Description
The MAX5109 8-bit DACs feature internal, nonvolatile
registers that store the DAC states for initialization dur-
ing power-up. This device consists of resistor-string
DACs, rail-to-rail output buffers, a shift register, power-
on reset (POR) circuitry, and volatile and nonvolatile
memory registers (Figure 1). The shift register decodes
the control and address bits, routing the data to the
proper registers. Writing data to a selected volatile reg-
ister immediately updates the DAC outputs.
The volatile registers retain data as long as the device
is powered. Removing power clears the volatile regis-
ters. The nonvolatile registers retain data even after
power is removed. On startup, when power is first
applied, data from the nonvolatile registers is trans-
ferred to the volatile registers to automatically initialize
the device. Read data from the nonvolatile or volatile
registers using the 2-wire serial interface.
DAC Operation
The MAX5109 uses a DAC matrix decoding architec-
ture that saves power. A resistor string divides the dif-
ference between the external reference voltages,
V
REFH_
and V
REFL_
. Row and column decoders select
the appropriate tap from the resistor string, providing
the equivalent analog voltage. The resistor string pre-
sents a code-independent input impedance to the ref-
erence and guarantees a monotonic output. Figure 2
shows a simplified diagram of one DAC.
Output Buffer Amplifiers
The MAX5109 analog outputs are internally buffered by
precision unity-gain amplifiers. The outputs swing from
GND to V
DD
with a V
REFL_
-to-V
REFH_
output transition.
The amplifier outputs typically settle to ±0.5 LSB in 8µs
when loaded with 5kΩ in parallel with 100pF.
MAX5109
Nonvolatile, Dual, 8-Bit DACs with 2-Wire Serial
Interface
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