© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 23
1 Publication Order Number:
MC100LVEP111/D
MC100LVEP111
2.5V / 3.3V 2:1:10
Differential ECL/PECL/HSTL
Clock Driver
Description
The MC100LVEP111 is a low skew 2:1:10 differential driver, designed
with clock distribution in mind, accepting two clock sources into an input
multiplexer. The PECL input signals can be either differential or
single−ended (if the V
BB
output is used). HSTL inputs can be used when
the LVEP111 is operating under PECL conditions.
The LVEP111 specifically guarantees low output−to−output skew.
Optimal design, layout, and processing minimize skew within a device and
from device to device.
To ensure tightest skew, both sides of differential outputs identically
terminate into 50 W even if only one output is being used. If an output
pair is unused, both outputs may be left open (unterminated) without
affecting skew.
The MC100LVEP111, as with most other ECL devices, can be
operated from a positive V
CC
supply in PECL mode. This allows the
LVEP111 to be used for high performance clock distribution in +3.3 V or
+2.5 V systems. Single−ended CLK input operation is limited to a V
CC
≥
3.0 V in PECL mode, or V
EE
v −3.0 V in NECL mode when using VBB
(See Figure 11). Full operating range is available when using an external
voltage reference (See Figure 10). Designers can take advantage of the
LVEP111’s performance to distribute low skew clocks across the
backplane or the board.
Features
• 85 ps Typical Device−to−Device Skew
• 20 ps Typical Output−to−Output Skew
• Jitter Less than 1 ps RMS
• Additive RMS Phase Jitter: 60 fs @ 156.25 MHz, Typ.
• Maximum Frequency > 3 GHz Typical
• V
BB
Output
• 430 ps Typical Propagation Delay
• The 100 Series Contains Temperature Compensation
• PECL and HSTL Mode Operating Range: V
CC
= 2.375 V to 3.8 V
with V
EE
= 0 V
• NECL Mode Operating Range: V
CC
= 0 V
with V
EE
= −2.375 V to −3.8 V
• Open Input Default State
• LVDS Input Compatible
• Fully Compatible with MC100EP111
• These are Pb−Free Devices
32
1
LQFP−32
FA SUFFIX
CASE 873A
MARKING
DIAGRAMS*
MC100
AWLYYWWG
LVEP111
www.onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
ORDERING INFORMATION
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G or G = Pb−Free Package
QFN32
MN SUFFIX
CASE 488AM
32
1
MC100
LVEP111
AWLYYWW
G
1
