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952906BFLF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23
10
Integrated
Circuit
Systems, Inc.
ICS952906A
1236A—08/06/07
Table 5: Asynchronous 3V66/PCI Frequency Table
Byte6 Bit7 Byte3 Bit7 3V66/PCI Frequency
0 0 66.66/33.33
0 1 80.00/40.00
1 0 72.73/36.36
I
2
C Table: Output Control Register
Control
Function
Bit 7
48MHz_0
2x output drive
0=2x drive RW 1
Bit 6
PCI ADIV
PCI Async Divider
Cntr
RW 0
Bit 5
Reserved Reserved RW 1
Bit 4
3V66_0 Output Control RW 1
Bit 3
Reserved Reserved RW 1
Bit 2
PCICLK_F2
Output Control RW 1
Bit 1
PCICLK_F1
Output Control RW 1
Bit 0
PCICLK_F0 Output Control RW 1
I
2
C Table: Reserved Register
Control
Function
Bit 7
Reserved Reserved RW 0
Bit 6
Mode Sel1 RW 0
Bit 5
Mode Sel0 RW 0
Bit 4
3V66_2 Output Control RW 1
Bit 3
M PLL2 Div3 RW X
Bit 2
M PLL2 Div2 RW X
Bit 1
M PLL2 Div1 RW X
Bit 0
M PLL2 Div0 RW X
--
See Table 4: Mode Selection Table
Disable Enable
Disable Enable
Disable Enable
--
Disable Enable
AGP/2 PLL3 Freq/24
Disable Enable
--
The decimal representation of M PLL2 Div
(3:0) + 2 is equal to REF divider value for
PLL2
01
01
-
-
-
-
PWD
7
Byte 5 Pin # Name Type
PWD
- 2x drive normal
Name TypeByte 4 Pin #
PLL Mode Selection
Bits
M Divider
Programming bits for
Async mode 2&3
-
25
-
-
-
29
-
9
8
-
Table 4: Mode Selection Table
Mode Standard Overclock Mode(I) CPU Overclock Mode(II) Graphic Overclock Mode(III)
IIC Control
Byte 5 bit(6:5) = 00 Byte 5 bit(6:5) = 01 Byte 5 bit(6:5) = 10
25MHz From?
PLL3 PLL3 PLL1
3V66/PCI From?
PLL1 (Needed to be align w/ CPU) PLL3 PLL3
Spreading
CPU/3V66/PCI have spread Only CPU clocks have spread. Only CPU clocks have spread.
I
2
C Table: Vendor & Revision ID Register
Control
Function
Bit 7
ASEL0 3V66/PCI Freq Select RW 0
Bit 6
N PLL2 Div6 RW X
Bit 5
N PLL2 Div5 RW X
Bit 4
N PLL2 Div4 RW X
Bit 3
N PLL2 Div3 RW X
Bit 2
N PLL2 Div2 RW X
Bit 1
N PLL2 Div1 RW X
Bit 0
N PLL2 Div0 RW X
The decimal representation of N PLL2 Div
(6:0) + 8 is equal to VCO divider value for
PLL2.
Byte 6 Pin # Name
-
-
-
PWD
-
-
N Divider
Programming bits for
Async mode 2&3
-
-
-
See Table 5: Async AGP/PCI Freq Table
01Type
11
Integrated
Circuit
Systems, Inc.
ICS952906A
1236A—08/06/07
I
2
C Table: Vendor & Revision ID Register
Control
Function
Bit 7
RID3 R X
Bit 6
RID2 R X
Bit 5
RID1 R X
Bit 4
RID0 R X
Bit 3
VID3 R 0
Bit 2
VID2 R 0
Bit 1
VID1 R 0
Bit 0
VID0 R 1
I
2
C Table: Byte Count Register
Control
Function
Bit 7
BC7 RW 0
Bit 6
BC6 RW 0
Bit 5
BC5 RW 0
Bit 4
BC4 RW 0
Bit 3
BC3 RW 1
Bit 2
BC2 RW 1
Bit 1
BC1 RW 1
Bit 0
BC0 RW 1
I
2
C Table: Watchdog Timer Register
Control
Function
Bit 7
WD7 WD Timer Bit 7 RW 0
Bit 6
WD6 WD Timer Bit 6 RW 0
Bit 5
WD5 WD Timer Bit 5 RW 0
Bit 4
WD4 WD Timer Bit 4 RW 0
Bit 3
WD3 WD Timer Bit 3 RW 1
Bit 2
WD2 WD Timer Bit 2 RW 0
Bit 1
WD1 WD Timer Bit 1 RW 1
Bit 0
WD0 WD Timer Bit 0 RW 1
I
2
C Table: VCO Control Select Bit & WD Timer Control Register
Control
Function
Bit 7
M/NEN
M/N Programming
Enable
RW 0
Bit 6
WDEN Watchdog Enable R 0
Bit 5
WDFSEN
WD Safe Frequency
Mode
RW 0
Bit 4
WD SF4 RW 0
Bit 3
WD SF3 RW 0
Bit 2
WD SF2 RW 0
Bit 1
WD SF1 RW 0
Bit 0
WD SF0 RW 0
--
1
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
0
--
--
--
--
1
--
--
--
PWD
01
Disable Enable
01Byte 9 Pin # Name Type
Disable Enable
Latched FS/Byte0
These bits represent X*290ms the
watchdog timer waits before it goes to
alarm mode. Default is 11 x 293ms =
3.2s.
Writing to these bit will configure the safe
frequency as Byte0 bit (4:0).
WD B10 b(4:0)
-
Watch Dog Safe Freq
Programming bits
-
-
-
-
-
-
PWD
-
Byte 10 Pin # Name Type
-
-
-
-
-
PWD
-
Byte Count
Programming b(7:0)
-
-
-
-
-
-
-
Type
-
Type
-
VENDOR ID
-
-
NameByte 8 Pin #
PWD
-
REVISION ID
-
-
-
Byte 7 Pin # Name 0
-
-
-
12
Integrated
Circuit
Systems, Inc.
ICS952906A
1236A—08/06/07
I
2
C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div8 N Divider Prog bit 8 RW X
Bit 6
M Div6 RW X
Bit 5
M Div5 RW X
Bit 4
M Div4 RW X
Bit 3
M Div3 RW X
Bit 2
M Div2 RW X
Bit 1
M Div1 RW X
Bit 0
M Div0 RW X
I
2
C Table: VCO Frequency Control Register
Control
Function
Bit 7
N Div7 RW X
Bit 6
N Div6 RW X
Bit 5
N Div5 RW X
Bit 4
N Div4 RW X
Bit 3
N Div3 RW X
Bit 2
N Div2 RW X
Bit 1
N Div1 RW X
Bit 0
N Div0 RW X
I
2
C Table: Spread Spectrum Control Register
Control
Function
Bit 7
SSP7 RW X
Bit 6
SSP6 RW X
Bit 5
SSP5 RW X
Bit 4
SSP4 RW X
Bit 3
SSP3 RW X
Bit 2
SSP2 RW X
Bit 1
SSP1 RW X
Bit 0
SSP0 RW X
I
2
C Table: Spread Spectrum Control Register
Control
Function
Bit 7
Reserved Reserved R 0
Bit 6
Reserved Reserved R 0
Bit 5
SSP13 RW X
Bit 4
SSP12 RW X
Bit 3
SSP11 RW X
Bit 2
SSP10 RW X
Bit 1
SSP9 RW X
Bit 0
SSP8 RW X
01
-
01PWD
0
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
These Spread Spectrum bits in Byte 13
and 14 will program the spread
pecentage. It is recommended to use
ICS Spread % table for spread
programming.
01
--
-
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(8:0)+8] /
[MDiv(6:0)+2]
1
The decimal representation of M and N
Divier in Byte 11 and 12 will configure the
VCO frequency. Default at power up =
latch-in or Byte 0 Rom table. VCO
Frequency = 14.318 x [NDiv(8:0)+8] /
[MDiv(6:0)+2]
-
-
Spread Spectrum
Programming b(13:8)
-
-
-
-
-
PWD
-
Byte 14 Pin # Name Type
PWD
-
Spread Spectrum
Programming b(7:0)
-
-
-
-
-
-
-
Name Type
-
-
Byte 13 Pin #
PWD
-
N Divider
Programming b(8:0)
-
-
-
-
-
Byte 12 Pin # Name Type
-
M Divider
Programming bits
-
-
-
-
-
-
-
Byte 11 Pin # Name Type
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P23

952906BFLF

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Buy 952906BFLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products PC MAIN CLOCK
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