2
Integrated
Circuit
Systems, Inc.
ICS952906A
1236A—08/06/07
Pin Description
PIN # PIN NAME PIN TYPE DESCRIPTION
1 *FS1/REF0 I/O Frequency select latch input pin / 14.318 MHz reference clock.
2 **FS0/REF1 I/O Frequency select latch input pin / 14.318 MHz reference clock.
3 VDDREF PWR Ref, XTAL power supply, nominal 3.3V
4 X1 IN Crystal input, Nominally 14.318MHz.
5 X2 OUT Crystal output, Nominally 14.318MHz
6 GND PWR Ground pin.
7 **FS2/PCICLK_F0 I/O Frequency select latch input pin / 3.3V PCI free running clock output.
8 **FS4/PCICLK_F1 I/O Frequency select latch input pin / 3.3V PCI free running clock output.
9 PCICLK_F2 OUT Free running PCI clock not affected by PCI_STOP# .
10 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
11 GND PWR Ground pin.
12 **MODE/PCICLK0 I/O
Function select latch input pin, 0=Desktop Mode (pin 44/45 are outputs), 1=Mobile Mode (pin44/45 are STOP
inputs) / PCI clock output.
13 PCICLK1 OUT PCI clock output.
14 PCICLK2 OUT PCI clock output.
15 PCICLK3 OUT PCI clock output.
16 PCICLK4 OUT PCI clock output.
17 VDDPCI PWR Power supply for PCI clocks, nominal 3.3V
18 GND PWR Ground pin.
19 PCICLK5 OUT PCI clock output.
20 PCICLK6 OUT PCI clock output.
21 **FS3/48MHz I/O Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
22 **Sel24_48#/24_48MHz I/O Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24MHz, 0 = 48MHz.
23 GND PWR Ground pin.
24 VDD48 PWR Power pin for the 48MHz output.3.3V
25 3V66_2 OUT 3.3V 66.66MHz clock output
26 3V66_1 OUT 3.3V 66.66MHz clock output
27 VDD3V66 PWR Power pin for the 3.3V 66MHz clocks.
28 GND PWR Ground pin.
29 3V66_0 OUT 3.3V 66.66MHz clock output
30 Reset# OUT
Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is
active low.
31 SCLK IN Clock pin of SMBus circuitry, 5V tolerant.
32 SDATA I/O Data pin for SMBus circuitry, 3.3V tolerant.
33 VttPWR_GD/PD# IN
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid and are ready
to be sampled. This is an active high input. / Asynchronous active low input pin used to power down the
device into a low power state.
34 VDD2.5 PWR Power supply, nominal 2.5V
35 25Mhz_1 OUT 25MHz clock output, 2.5V
36 25Mhz_0 OUT 25MHz clock output, 2.5V
37 GND PWR Ground pin.
38 CPUCLKC0 OUT
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
39 CPUCLKT0 OUT
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias.
40 VDDCPU PWR Supply for CPU clocks, 3.3V nominal
41 CPUCLKC1 OUT
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
42 CPUCLKT1 OUT
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias.
43 GND PWR Ground pin.
44 CPUCLKC_ITP/(CPU_STOP#) I/O
Complementary clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias. / Stops all CPUCLK besides the free running clocks
45 CPUCLKT_ITP/(PCI_STOP#) I/O
True clock of differential pair CPU outputs. These are current mode outputs. External resistors are required
for voltage bias. / Stops all PCICLK besides the free running clocks
46 IREF OUT
This pin establishes the reference current for the differential current-mode output pairs. This pin requires a
fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard
value.
47 GND PWR Ground pin.
48 VDDA PWR 3.3V power for the PLL core.
