© Semiconductor Components Industries, LLC, 2013
July, 2013 − Rev. 2
1 Publication Order Number:
NLSX3018/D
NLSX3018
8-Bit 100 Mb/s Configurable
Dual-Supply Level
Translator
The NLSX3018 is a 8−bit configurable dual−supply bidirectional
level translator without a direction control pin. The I/O V
CC
− and I/O
V
L
−ports are designed to track two different power supply rails, V
CC
and V
L
respectively. The V
CC
supply rail is configurable from 1.3 V
to 4.5 V while the V
L
supply rail is configurable from 0.9 V to (V
CC
− 0.4) V. This allows lower voltage logic signals on the V
L
side to be
translated into higher voltage logic signals on the V
CC
side, and
vice−versa. Both I/O ports are auto−sensing; thus, no direction pin is
required.
The Output Enable (EN) input, when Low, disables both I/O ports
by putting them in 3−state. This significantly reduces the supply
currents from both V
CC
and V
L
. The EN signal is designed to track
V
L
.
Features
• Wide High−Side V
CC
Operating Range: 1.3 V to 4.5 V
Wide Low−Side V
L
Operating Range: 0.9 V to (V
CC
− 0.4) V
• High−Speed with 100 Mb/s Guaranteed Date Rate for V
L
> 1.6 V
• Low Bit−to−Bit Skew
• Overvoltage Tolerant Enable and I/O Pins
• Non−preferential Powerup Sequencing
• Small packaging: 4.0 mm x 2.0 mm UDFN20
• This is a Pb−Free Device
Typical Applications
• Mobile Phones, PDAs, Other Portable Devices
PIN ASSIGNMENT
(Top View)
I/O V
L
2
I/O V
L
3
I/O V
L
4
V
L
I/O V
CC
1
I/O V
CC
2
I/O V
CC
3
I/O V
CC
4
V
CC
I/O V
L
1
I/O V
CC
8I/O V
L
8
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
EN
I/O V
L
5
I/O V
L
6
I/O V
L
7
GND
I/O V
CC
5
I/O V
CC
6
I/O V
CC
7
MARKING
DIAGRAMS
http://onsemi.com
UDFN20
MU SUFFIX
CASE 517AK
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
LA = Specific Device Code
M = Date Code
G = Pb−Free Package
(Note: Microdot may be in either location)
LAM
G
20
1
NLSX3018
AWLYYWWG
SOIC−20
DW SUFFIX
CASE 751D
NLSX
3018
ALYWG
G
TSSOP−20
DT SUFFIX
CASE 948E
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
