MAX4929E
HDMI 2:1 Low-Frequency Translating Switch
6 _______________________________________________________________________________________
Pin Description
PIN
QSOP TQFN
NAME FUNCTION
1 19 HPDO2 Hot-Plug Detect Output 2. Translate logic level of HPD to V+ compatible (see Table 2).
2 20 HPIR2 Hot-Plug Interrupt Request 2
3 1 SDA2 Serial Data Input. SDA Mux Input 2.
4 2 SCL2 Serial Clock Input. SCL Mux Input 2.
5 3 HPDO1 Hot-Plug Detect Output 1. Translate logic level of HPD to V+ compatible (see Table 2).
6 4 HPIR1 Hot-Plug Interrupt Request 1
7 5 SDA1 Serial Data Input. SDA Mux Input 1.
8 6 SCL1 Serial Clock Input. SCL Mux Input 1.
9 7 V+ Positive Supply Voltage. Bypass V+ to GND with a 0.1µF or greater ceramic capacitor.
10 8 CLP
Clamp-Voltage Reference. Clamp the maximum voltage of SCLO and SDAO. Bypass
CLP to GND with a 0.1µF or greater ceramic capacitor (see Figure 6 and the Typical
Operating Circuit).
11 9 VL
Logic Supply for HIZ_, SEL, HPD, HPIRO. Bypass VL to GND with a 0.1µF or greater
ceramic capacitor. VL should have the same voltage level as any MCU interface.
12 10 SEL Select Input. Logic input for Mux connection (see Table 1).
13 11 SCLO SCL Mux Output. Connect SCLO to EDID EPROM.
14 12 SDAO SDA Mux Output. Connect SDAO to EDID EPROM.
15 13 HPIRO
Hot-Plug Interrupt Request Output. Translate logic level of HPIR_ to VL compatible
(see Table 3).
16 14 HPD Hot-Plug Detect Input. Logic level on HPD is compatible with MCU.
17 15 HIZ2 Enable Input 2 (see Table 4).
18 16 HIZ1 Enable Input 1 (see Table 4).
19 17 GND Ground
20 18 EXESD External ESD Discharge. Connect 0.1µF capacitor from EXESD to GND.
— EP EP Exposed Paddle. Connect EP to GND or leave EP unconnected.
