Philips Semiconductors Product specification
N-channel TrenchMOS transistor PSMN009-100W
AVALANCHE ENERGY LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
E
AS
Non-repetitive avalanche Unclamped inductive load, I
AS
= 100 A; - 650 mJ
energy t
p
= 100 µs; T
j
prior to avalanche = 25˚C;
V
DD
≤ 50 V; R
GS
= 50 Ω; V
GS
= 5 V; refer to
fig:15
I
AS
Non-repetitive avalanche - 100 A
current
THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS TYP. MAX. UNIT
R
th j-mb
Thermal resistance junction - 0.5 K/W
to mounting base
R
th j-a
Thermal resistance junction in free air 45 - K/W
to ambient
ELECTRICAL CHARACTERISTICS
T
j
= 25˚C unless otherwise specified
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
V
(BR)DSS
Drain-source breakdown V
GS
= 0 V; I
D
= 0.25 mA; 100 - - V
voltage T
j
= -55˚C 89 - - V
V
GS(TO)
Gate threshold voltage V
DS
= V
GS
; I
D
= 1 mA 2.0 3.0 4.0 V
T
j
= 175˚C 1.0 - - V
T
j
= -55˚C - - 6 V
R
DS(ON)
Drain-source on-state V
GS
= 10 V; I
D
= 25 A - 6.7 9 mΩ
resistance T
j
= 175˚C - 15 25 mΩ
I
GSS
Gate source leakage current V
GS
= ±10 V; V
DS
= 0 V - 2 100 nA
I
DSS
Zero gate voltage drain V
DS
= 100 V; V
GS
= 0 V; - 0.05 10 µA
current T
j
= 175˚C - - 500 µA
Q
g(tot)
Total gate charge I
D
= 100 A; V
DD
= 80 V; V
GS
= 10 V - 214 - nC
Q
gs
Gate-source charge - 45 - nC
Q
gd
Gate-drain (Miller) charge - 91 - nC
t
d on
Turn-on delay time V
DD
= 50 V; R
D
= 2 Ω; - 40 - ns
t
r
Turn-on rise time V
GS
= 10 V; R
G
= 5.6 Ω - 100 - ns
t
d off
Turn-off delay time Resistive load - 260 - ns
t
f
Turn-off fall time - 100 - ns
L
d
Internal drain inductance Measured from tab to centre of die - 3.5 - nH
L
d
Internal drain inductance Measured from drain lead to centre of die - 4.5 - nH
L
s
Internal source inductance Measured from source lead to source - 7.5 - nH
bond pad
C
iss
Input capacitance V
GS
= 0 V; V
DS
= 25 V; f = 1 MHz - 9000 - pF
C
oss
Output capacitance - 1000 - pF
C
rss
Feedback capacitance - 650 - pF
October 1999 2 Rev 1.100
