Obsolete Product(s) - Obsolete Product(s)
Equivalent circuit of inputs and outputs STP16CL596
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2.1 Truth table
Table 3. Truth table
Note: OUT0 to OUT15 = ON when Dn = H; OUT0 to OUT15 = OFF when Dn = L.
2.2 Timing diagram
Note: Note: The latches circuit holds data when the LE terminal is Low.
When the LE terminal is at High level, latch circuit doesn’t hold the data it passes from the input
to the output.
When the OE
terminal is at Low level, output terminals OUT0 to OUT15 respond to the data,
either ON or OFF.
When the OE
terminal is at High level, it switches off all the data on the output terminal.
Clock LE OE SERIAL-IN OUT0 .................. OUT7 .................. OUT15 SDO
H L Dn Dn ..... Dn -7 ..... Dn -15 Dn -15
L L Dn + 1 No Change Dn -14
H L Dn + 2 Dn -2 ..... Dn -5 ..... Dn -13 Dn -13
X L Dn + 3 Dn -2 ..... Dn -5 ..... Dn -13 Dn -13
X L Dn + 3 ON Dn -13
Figure 7. Timing diagram - normal mode
