85354AK-01 10 REV. A JANUARY 16, 2008
ICS85354-01
DUAL 2:1/1:2
DIFFERENTIAL-TO-LVPECL/ECL MULTIPLEXER
PRELIMINARY
APPLICATION INFORMATION
Figure 1
shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF
in the center of the input voltage swing. For example, if the
input clock swing is only 2.5V and V
CC
= 3.3V, V_REF should be
1.25V and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Sin
le Ended Clock Input
INx
nINx
VCC
INPUTS:
In/nIn INPUT:
For applications not requiring the use of the differential input,
both IN and nIN can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from IN to
ground.
LVCMOS C
ONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
