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843031AGLF

P1-P3P4-P6P7-P9P10-P12P13-P14
843031 REVISION A 11/5/15 7 ©2015 Integrated Device Technology, Inc.
843031 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
Figure 1. CRYSTAL INPUt INTERFACE
CRYSTAL INPUT INTERFACE
The 843031 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 1 below were determined using a 26.04167MHz, 18pF
parallel resonant crystal and were chosen to minimize the ppm
error. The optimum C1 and C2 values can be slightly adjusted
for different board layouts.
X1
18pF Parallel Cry stal
C1
12p
XTAL_OUT
XTAL_IN
C2
12p
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
FIGURE 2B. LVPECL OUTPUT T ERMINATIONFIGURE 2A. LVPECL OUTPUT T ERMINATION
drive 50Ω transmission lines.Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 2A and 2B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
843031 REVISION A 11/5/15 8 ©2015 Integrated Device Technology, Inc.
843031 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843051.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843051 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V
CC
= 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core)
MAX
= V
CC_MAX
* I
EE_TYP
= 3.465V * 105mA = 363.83mW
• Power (outputs)
MAX
= 30mW/Loaded Output pair
Total Power
_MAX
(3.465V, with all outputs switching) = 363.8mW + 30mW = 393.8mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for the devices is 125°C.
The equation for Tj is as follows: Tj = θ
JA
* Pd_total + T
A
Tj = Junction Temperature
θ
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ
JA
must be used. Assuming
a moderate air fl ow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.394W * 90.5°C/W = 105.65°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air fl ow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ
JA
FOR 8-PIN TSSOP, FORCED CONVECTION
θ
JA
by Velocity (Meters per Second)
0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W
843031 REVISION A 11/5/15 9 ©2015 Integrated Device Technology, Inc.
843031 Data Sheet FEMTOCLOCK
®
CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 4.
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a
termination
voltage of V
CC
- 2V.
• For logic high, V
OUT
= V
OH_MAX
= V
CC_MAX
– 0.9V
(V
CCO_MAX
- V
OH_MAX
)
= 0.9V
• For logic low, V
OUT
= V
OL_MAX
= V
CC_MAX
– 1.7V
(V
CCO_MAX
- V
OL_MAX
)
= 1.7V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OH_MAX
) = [(2V - (V
CC
_MAX
- V
OH_MAX
))
/R
L
] * (V
CC_MAX
- V
OH_MAX
) =
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V
OL_MAX
– (V
CC_MAX
- 2V))/R
L
] * (V
CC_MAX
- V
OL_MAX
) = [(2V - (V
CC
_MAX
- V
OL_MAX
))
/R
L
] * (V
CC_MAX
- V
OL_MAX
) =
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
FIGURE 3. LVPECL DRIVER CIRCUIT AND T ERMINATION
P1-P3P4-P6P7-P9P10-P12P13-P14

843031AGLF

Mfr. #:
Buy 843031AGLF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVPECL OUT SYNTHESIZER
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