ADT7484A/ADT7486A
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4
Table 5. ELECTRICAL CHARACTERISTICS (continued)
(T
A
=T
MIN
to T
MAX
, V
CC
=V
MIN
to V
MAX
, unless otherwise noted)
Parameter UnitMaxTypMinConditions
SST Timing
Bitwise Period, t
BIT
0.495 − 500
ms
High Level Time for Logic 1, t
H1
(Note 2)
t
BIT
Defined in Speed Negotiation 0.6 t
BIT
0.75 t
BIT
0.8 t
BIT
ms
High Level Time for Logic 0, t
H0
(Note 2)
0.2 t
BIT
0.25 t
BIT
0.4 t
BIT
ms
Time to Assert SST High for
Logic 1, t
SU,
HIGH
− − 0.2 t
BIT
ms
Hold Time, t
HOLD
(Note 3) See SST Specification Rev 1.0 − − 0.5 t
BIT−M
ms
Stop Time, t
STOP
Device Responding to a Constant Low Level
Driven by Originator
1.25 t
BIT
2 t
BIT
2 t
BIT
ms
Time to Respond After a Reset,
t
RESET
− − 0.4 ms
Response Time to Speed
Negotiation After Powerup
Time after Powerup when Device Can
Participate in Speed Negotiation
− 500 −
ms
1. Guaranteed by design, not production tested.
2. Minimum and maximum bit times are relative to t
BIT
defined in the timing negotiation pulse.
3. Devices compatible with hold time specification as driven by SST originator.