LTC4267-3
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the classification current is re-enabled. C1 will discharge
through the PD circuitry and the P
OUT
pin will go to a high
impedance state.
Input Current Limit
IEEE 802.3af specifies a maximum inrush current and
also specifies a minimum load capacitor between the
V
PORTP
and P
OUT
pins. To control turn-on surge current
in the system, the LTC4267-3 integrates a dual level cur-
rent limit circuit with an onboard power MOSFET and
sense resistor to provide a complete inrush control cir
cuit
without additional external components
. At turn-on, the
LTC4267-3 will limit the input current to the low level,
allowing the load capacitor to ramp up to the line voltage
in a controlled manner.
The LTC4267-3 has been specifically designed to interface
with legacy PSEs which do not meet the inrush current
requirement of the IEEE 802.3af specification. At turn-on
the LTC4267-3 current limit is set to the lower level. After
C1 is charged up and the P
OUT
V
PORTN
voltage difference
is below the power good threshold, the LTC4267-3 switches
to the high level current limit. The dual level current limit
allows legacy PSEs with limited current sourcing capability
to power up the PD while also allowing the PD to draw full
power from an IEEE 802.3af PSE. The dual level current
limit also allows use of arbitrarily large load capacitors.
The IEEE 802.3af specification mandates that at turn-on
the PD not exceed the inrush current limit for more than
50ms. The LTC4267-3 is not restricted to the 50ms time
limit because the load capacitor is charged with a current
below the IEEE inrush current limit specification.
As the LTC4267-3 switches from the low to high level
current limit, the current will increase momentarily. This
current spike is a result of the LTC4267-3 charging the
last 1.5V at the high level current limit. When charging a
10µF capacitor, the current spike is typically 100µs wide
and 125% of the nominal low level current limit.
The LTC4267-3 stays in the high level current limit mode
until the input voltage drops below the UVLO turn-off
threshold. This dual level current limit provides the sys
-
tem designer with the flexibility to design PDs which are
compatible
with
legacy PSEs while also being able to take
advantage of the higher power allocation available in an
IEEE 802.3af system.
During the current limited turn on, a large amount of power
is dissipated in the power MOSFET. The LTC4267-3 PD
interface is designed to accept this thermal load and is
thermally protected to avoid damage to the onboard power
MOSFET. Note that in order to adhere to the IEEE 802.3af
standard, it is necessary for the PD designer to ensure
the PD steady state power consumption falls within the
limits shown in Table 2. In addition, the steady state cur
-
rent must be less than I
LIM_HI
.
Power Good
The LTC4267-3 PD Interface includes a power good circuit
(Figure 6) that is used to indicate that load capacitor C1
is fully charged and that the switching regulator can start
operation. The power good circuit monitors the voltage
across the internal UVLO power MOSFET and PWRGD is
asserted when the voltage falls below 1.5V. The power
good circuit includes hysteresis to allow the LTC4267-3 to
operate near the current limit point without inadvertently
disabling PWRGD. The MOSFET voltage must increase to
3V before PWRGD is disabled.
If a sudden increase in voltage appears on the input line,
this voltage step will be transferred through capacitor C1
and appear across the power MOSFET. The response of
the LTC4267-3 will depend on the magnitude of the volt
-
age step, the rise time of the step, the value of capacitor
C1
and the switching regulator load. For fast rising inputs,
Figure 5. LTC4267-3 V
PORTN
Undervoltage Lockout
C1
5µF
MIN
V
PORTN
V
PORTP
P
OUT
PGND
LTC4267-3
42673 F05
TO
PSE
UNDERVOLTAGE
LOCKOUT
CIRCUIT
CURRENT-LIMITED
TURN ON
+
INPUT LTC4267-3
VOLTAGE POWER MOSFET
0V TO UVLO* OFF
>UVLO* ON
*UVLO INCLUDES HYSTERESIS
RISING INPUT THRESHOLD –36V
FALLING INPUT THRESHOLD –30.5V
applicaTions inForMaTion
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applicaTions inForMaTion
PWRGD
C1
5µF
MIN
V
PORTN
P
OUT
1.125V
300k
300k
R9
100k
LTC4267-3
THERMAL SHUTDOWN
UVLO
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TO
PSE
+
+
+
I
TH
/RUN
PGND
PGND
Figure 6. LTC4267-3 Power Good
Figure 7. Power Good Interface Examples
42673 F07
LTC4267-3
V
PORTN
P
OUT
PGND
V
PORTP
I
TH
/RUN
TO
PSE
–48V
+
C1
5µF
100V
ALTERNATE ACTIVE-HIGH ENABLE FOR P
VCC
PIN
C15 AND C17 OPTIONAL
SEE APPLICATIONS INFORMATION SECTION
ACTIVE-HIGH ENABLE FOR RUN PIN WITH INTERNAL PULL-UP
R18
10k
R9
100k
D6
MMBD4148
C15
0.047µF
Q1
FMMT2222
PWRGD
PGND
LTC4267-3
V
PORTN
P
OUT
PGND
V
PORTP
P
VCC
TO
PSE
–48V
+
C1
5µF
100V
R18
10k
R9
100k
D6
MMBD4148
C15
0.047µF
Q1
FMMT2222
PWRGD
PGND
R
START
C
PVCC
C17
the LTC4267-3 will attempt to quickly charge capacitor C1
using an internal secondary current limit circuit. In this
scenario, the PSE current limit should provide the overall
limit for the circuit. For slower rising inputs, the 375mA
current limit in the LTC4267-3 will set the charge rate of
the capacitor C1. In either case, the PWRGD signal may
go inactive briefly while the capacitor is charged up to the
new line voltage. In the design of a PD, it is necessary
to determine if a step in the input voltage will cause the
PWRGD signal to go inactive and how to respond to this
event. In some designs, it may be desirable to filter the
PWRGD signal so that intermittent power bad conditions
are ignored. Figure 7 demonstrates a method to insert a
lowpass filter on the power good interface.
For PD designs that use a large load capacitor and also
consume a lot of power, it is important to delay activation
of the switching regulator with the PWRGD signal. If the
regulator is not disabled during the current-limited turn-on
sequence, the PD circuitry will rob current intended for
charging up the load capacitor and create a slow rising
input, possibly causing the LTC4267-3 to go into thermal
shutdown.
The PWRGD pin connects to an internal open drain, 100V
transistor capable of sinking 1mA. Low impedance to
V
PORTN
indicates power is good. PWRGD is high imped-
ance during signature and classification probing and in
the event of a thermal overload.
During turn-off, PWRGD
is deactivated when the input voltage drops below 30V.
In addition, PWRGD may go active briefly at turn-on for
fast rising input waveforms. PWRGD is referenced to the
V
PORTN
pin and when active, will be near the V
PORTN
po-
tential. Connect the PWRGD pin to the switching regulator
circuitr
y as shown in Figure 7.
PD Interface Thermal Protection
The LTC4267-3 PD Interface includes thermal overload
protection in order to provide full device functionality in
a miniature package while maintaining safe operating
temperatures. Several factors create the possibility of
significant power dissipation within the LTC4267-3. At
turn-on, before the load capacitor has charged up, the
instantaneous power dissipated by the LTC4267-3 can be
as much as 10W. As the load capacitor charges up, the
power dissipation in the LTC4267-3 will decrease until it
reaches a steady-state value dependent on the DC load
current. The size of the load capacitor determines how fast
the power dissipation in the LTC4267-3 will subside. At
room temperature, the LTC4267-3 can typically handle load
capacitors as large as 800µF without going into thermal
shutdown. With large load capacitors, the LTC4267-3 die
temperature will increase by as much as 50°C during a
single turn-on sequence. If for some reason power were
removed from the part and then quickly reapplied so that
the LTC4267-3 had to charge up the load capacitor again,
the temperature rise would be excessive if safety precau
-
tions were not implemented.
The LTC4267-3
PD interface protects itself from thermal
damage by monitoring the die temperature. If the die
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applicaTions inForMaTion
temperature exceeds the overtemperature trip point, the
current is reduced to zero and very little power is dissi-
pated in the part until it cools below the overtemperature
set point. Once the LTC4267-3 has charged up the load
capacitor and the PD is powered and running, there will
be minor residual heating due to the DC load current of
the PD flowing through the internal MOSFET.
During classification, excessive heating of the LTC4267-3
can occur if the PSE violates the 75ms probing time limit.
To protect the LTC4267-3, thermal overload circuitry will
disable classification current if the die temperature exceeds
the overtemperature trip point. When the die cools down
below the trip point, classification current is re-enabled.
The PD is designed to operate at a high ambient tem-
perature and with the maximum allowable supply (57V).
However,
there is a limit to the size of the load capacitor
that can be charged up before the LTC4267-3 reaches the
overtemperature trip point. Hitting the overtemperature trip
point intermittently does not harm the LTC4267-3, but it
will delay the completion of capacitor charging. Capacitors
up to 200µF can be charged without a problem over the
full operating temperature range.
Switching Regulator Main Control Loop
Due to space limitations, the basics of current mode
DC/DC conversion will not be discussed here. The reader
is referred to the detail treatment in Application Note 19
or in texts such as Abraham Pressman’s Switching Power
Supply Design.
In a Power over Ethernet System, the majority of applica-
tions involve an isolated power supply design. This means
that the output power supply does not have any DC elec-
trical path to the PD interface or the switching regulator
primary. The DC isolation is achieved typically through a
transformer in the forward path and an opto-isolator in
the feedback path or a third winding in the transformer.
The typical application circuit shown on the front page
of the data sheet represents an isolated design using an
opto-isolator. In applications where a nonisolated topol-
ogy is desired, the LTC4267-3 features a feedback port
and an internal error amplifier that can be enabled for this
specific application.
In the typical application circuit (Figure 11), the isolated
topology employs an external resistive voltage divider to
present a fraction of the output voltage to an external er
-
ror amplifier. The error amplifier responds by pulling an
analog current through the input LED on an opto-isolator.
The collector of the opto-isolator output presents a cor
-
responding current into the I
TH
/RUN pin via a series diode.
This method generates a feedback voltage on the I
TH
/RUN
pin while maintaining isolation.
The voltage on the I
TH
/RUN pin controls the pulse-width
modulator formed by the oscillator, current comparator,
and RS latch. Specifically, the voltage at the I
TH
/RUN pin
sets the current comparators trip threshold. The current
comparator monitors the voltage across a sense resistor
in series with the source terminal of the external N-Channel
MOSFET. The LTC4267-3 turns on the external power
MOSFET when the internal free-running 300kHz oscillator
sets the RS latch. It turns off the MOSFET when the cur
-
rent comparator resets the latch or when 80%
duty cycle
is reached, whichever happens first. In this way, the peak
current levels through the flyback transformers primary
and secondary are controlled by the I
TH
/RUN voltage.
In applications where a nonisolated topology is desir-
able (
Figure 11), an external resistive voltage divider can
present a fraction of the output voltage directly to the
V
FB
pin of the LTC4267-3. The divider must be designed
so when the output is at its desired voltage, the V
FB
pin
voltage will equal the 800mV onboard internal reference.
The internal error amplifier responds by driving the I
TH
/
RUN pin. The LTC4267-3 switching regulator performs in
a similar manner as described previously.
Regulator Start-Up/Shutdown
The LTC4267-3 switching regulator has two shutdown
mechanisms to enable and disable operation: an un
-
dervoltage lockout on the P
VCC
supply pin and a forced
shutdown whenever external circuitry drives the I
TH
/RUN
pin low. The LTC4267-3 switcher transitions into and out
of shutdown according to the state diagram (Figure 8).
It is important not to confuse the undervoltage lockout
of the PD interface at V
PORTN
with that of the switching
regulator at P
VCC
. They are independent functions.

LTC4267CDHC-3#PBF

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Power Switch ICs - POE / LAN IEEE802.3af PD w/Switching Reg.
Lifecycle:
New from this manufacturer.
Delivery:
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