© 2000 Fairchild Semiconductor Corporation DS006436 www.fairchildsemi.com
August 1986
Revised March 2000
DM74LS670 3-STATE 4-by-4 Register File
DM74LS670
3-STATE 4-by-4 Register File
General Description
These register files are organized as 4 words of 4 bits
each, and separate on-chip decoding is provided for
addressing the four word locations to either write-in or
retrieve data. This permits writing into one location, and
reading from another word location, simultaneously.
Four data inputs are available to supply the word to be
stored. Location of the word is determined by the write
select inputs A and B, in conjunction with a write-enable
signal. Data applied at the inputs should be in its true form.
That is, if a high level signal is desired from the output, a
high level is applied at the data input for that particular bit
location. The latch inputs are arranged so that new data
will be accepted only if both internal address gate inputs
are HIGH. When this condition exists, data at the D input is
transferred to the latch output. When the write-enable
input, G
W
, is HIGH, the data inputs are inhibited and their
levels can cause no change in the information stored in the
internal latches. When the read-enable input, G
R
, is HIGH,
the data outputs are inhibited and go into the high imped-
ance state.
The individual address lines permit direct acquisition of
data stored in any four of the latches. Four individual
decoding gates are used to complete the address for read-
ing a word. When the read address is made in conjunction
with the read-enable signal, the word appears at the four
outputs.
This arrangement—data entry addressing separate from
data read addressing and individual sense line — elimi-
nates recovery times, permits simultaneous reading and
writing, and is limited in speed only by the write time (27 ns
typical) and the read time (24 ns typical). The register file
has a non-volatile readout in that data is not lost when
addressed.
All inputs (except read enable and write enable) are buff-
ered to lower the drive requirements to one normal Series
DM74LS load, and input clamping diodes minimize switch-
ing transients to simplify system design. High speed, dou-
ble ended AND-OR-INVERT gates are employed for the
read-address function and have high sink current, 3-STATE
outputs. Up to 128 of these outputs may be wire-AND con-
nected for increasing the capacity up to 512 words. Any
number of these registers may be paralleled to provide n-
bit word length.
Features
■ For use as:
Scratch pad memory
Buffer storage between processors
Bit storage in fast multiplication designs
■ Separate read/write addressing permits simultaneous
reading and writing
■ Organized as 4 words of 4 bits
■ Expandable to 512 words of n-bits
■ 3-STATE versions of DM74LS170
■ Fast access times 20 ns typ
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Order Number Package Number Package Description
DM74LS670M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74LS670N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
