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DC and AC parameters M48T212V
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Table 13. Capacitance
Table 14. DC characteristics
Symbol Parameter
(1)(2)
1. Effective capacitance measured with power supply at 3.3V (M48T212V); sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
Min Max Unit
C
IN
Input capacitance 10 pF
C
OUT
(3)
3. Outputs deselected.
Input/output capacitance 10 pF
Sym Parameter Test condition
(1)
1. Valid for ambient operating temperature: T
A
= 0 to 70°C; V
CC
= 3.0 to 3.6V (except where noted).
M48T212V
Unit–85
Min Typ Max
I
LI
(2)
2. RSTIN1 and RSTIN2 internally pulled-up to V
CC
through 100KΩ resistor. WDI internally pulled-down to V
SS
through 100KΩ
resistor.
Input leakage current 0V ≤ V
IN
≤ V
CC
±1 µA
I
LO
(3)
3. Outputs deselected.
Output leakage current 0V ≤ V
OUT
≤ V
CC
±1 µA
I
CC
Supply current Outputs open 4 10 mA
I
CC1
Supply current (standby) TTL E = V
IH
3mA
I
CC2
Supply current (standby) CMOS E = V
CC
–0.2 2 mA
I
BAT
Battery current OSC ON
V
CC
= 0V
575 800 nA
Battery current OSC ON
(4)
4. I
BAT
(OSC ON) = Industrial Temperature Range - Grade 6 device.
950 1250 nA
Battery current OSC OFF 100 nA
V
IL
Input low voltage –0.3 0.8 V
V
IH
Input high voltage 2.0
V
CC
+
0.3
V
V
OL
Output low voltage I
OL
= 2.1mA 0.4 V
Output low voltage (open drain)
(5)
5. For IRQ/FT & RST pins (open drain).
I
OL
= 10mA 0.4 V
V
OH
Output high voltage I
OH
= –1.0mA 2.4 V
V
OHB
(6)
6. Conditioned outputs (E1
CON
- E2
CON
) can only sustain CMOS leakage currents in the battery back-up mode. Higher
leakage currents will reduce battery life.
V
OH
battery back-up I
OUT2
= –1.0µA 2.0 3.6 V
I
OU1
(7)
7. External SRAM must match TIMEKEEPER
®
supervisor chip V
CC
specification.
V
OUT
current (active) V
OUT1
> V
CC
–0.3 70 mA
I
OUT2
V
OUT
current (battery back-up) V
OUT2
> V
BAT
–0.3 100 µA
V
PFD
Power-fail deselect voltage 2.7 2.9 3.0 V
V
SO
Battery back-up switchover voltage
V
PFD
–
100mV
V
V
BAT
Battery voltage 3.0 V
