IRF710STRLPBF Datasheet IRF710SPBF, IRF710STRLPBF | P4-P6

www.vishay.com Document Number: 91042

4 S11-1048-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRF710S, SiHF710S

Vishay Siliconix

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 8 - Maximum Safe Operating Area

400

300

200

0

100

10

0

10

1

Capacitance (pF)

V

DS

,

Drain-to-Source Voltage (V)

C

iss

C

rss

C

oss

V

GS

= 0 V, f = 1 MHz

C

iss

= C

gs

+ C

gd

, C

ds

Shorted

C

rss

= C

gd

C

oss

= C

ds

+ C

gd

91042_05

Q

G

, Total Gate Charge (nC)

V

GS

, Gate-to-Source Voltage (V)

20

16

12

8

0

4

0

4

121086

V

DS

= 80 V

V

DS

= 200 V

For test circuit

see figure 13

V

DS

= 320 V

91042_06

I

D

= 2.0 A

2

10

-1

10

0

V

SD

, Source-to-Drain Voltage (V)

I

SD

, Reverse Drain Current (A)

0.4

1.2

1.00.80.6

25

°

C

150

°

C

V

GS

= 0 V

91042_07

1.4

100 µs

1 ms

10 ms

Operation in this area limited

by R

DS(on)

V

DS

, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

T

C

= 25 °C

T

J

= 150 °C

Single Pulse

10

2

5

0.1

1

2

5

10

2

5

25

1

25

10

25

10

2

10

3

91042_08

Document Number: 91042 www.vishay.com

S11-1048-Rev. C, 30-May-11 5

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRF710S, SiHF710S

Vishay Siliconix

Fig. 9 - Maximum Drain Current vs. Case Temperature

Fig. 10a - Switching Time Test Circuit

Fig. 10b - Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

I

D

, Drain Current (A)

T

C

, Case Temperature (°C)

0.0

0.4

0.8

1.2

1.6

2.0

25 1501251007550

91042_09

Pulse width ≤ 1 µs

Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

10

1

0.1

10

-2

10

-5

10

-4

10

-3

10

-2

0.1

110

P

DM

t

1

t

2

t

1

, Rectangular Pulse Duration (s)

Thermal Response (Z

thJC

)

Notes:

1. Duty Factor, D = t

1

/t

2

2. Peak T

j

= P

DM

x Z

thJC

+ T

C

Single Pulse

(Thermal Response)

0 − 0.5

0.2

0.1

0.05

0.02

0.01

91042_11

www.vishay.com Document Number: 91042

6 S11-1048-Rev. C, 30-May-11

This document is subject to change without notice.

THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT

www.vishay.com/doc?91000

IRF710S, SiHF710S

Vishay Siliconix

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

R

g

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

10 V

Vary t

p

to obtain

required I

AS

I

AS

V

DS

V

DD

V

DS

t

p

300

0

50

100

150

200

250

25 150

125

10075

50

Starting T

J

, Junction Temperature (°C)

E

AS

, Single Pulse Energy (mJ)

Bottom

To p

I

D

0.89 A

1.3 A

2.0 A

V

DD

= 50 V

91042_12c

Q

GS

Q

GD

Q

G

V

G

Charge

10 V

D.U.T.

3 mA

V

GS

V

DS

I

G

I

D

0.3 µF

0.2 µF

50 kΩ

12 V

Current regulator

Current sampling resistors

Same type as D.U.T.

+

-

IRF710STRLPBF

IRF710STRLPBF

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