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MAX1162BEUB+T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
10 ______________________________________________________________________________________
Digital Interface
Initialization after Power-Up and
Starting a Conversion
The digital interface consists of two inputs, SCLK and
CS, and one output, DOUT. A logic high on CS places
the MAX1162 in shutdown (AutoShutdown) and places
DOUT in a high-impedance state. A logic low on CS
places the MAX1162 in the fully powered mode.
To start a conversion, pull CS low. A falling edge on CS
initiates an acquisition. SCLK drives the A/D conversion
and shifts out the conversion results (MSB first) at DOUT.
Timing and Control
Conversion-start and data-read operations are con-
trolled by the CS and SCLK digital inputs (Figures 6
and 7). Ensure that the duty cycle on SCLK is between
40% and 60% at 4.8MHz (the maximum clock frequen-
cy). For lower clock frequencies, ensure that the mini-
mum high and low times are at least 65ns.
Conversions with SCLK rates less than 100kHz can
result in reduced accuracy due to leakage.
Note: Coupling between SCLK and the analog
inputs (AIN and REF) may result in an offset.
Variations in frequency, duty cycle, or other aspects
of the clock signal’s shape result in changing offset.
A CS falling edge initiates an acquisition sequence.
The analog input is stored in the capacitive DAC,
DOUT changes from high impedance to logic low, and
the ADC begins to convert after the sixth clock cycle.
SCLK drives the conversion process and shifts out the
conversion result on DOUT.
SCLK begins shifting out the data (MSB first) after the
falling edge of the 8th SCLK pulse. Twenty-four falling
clock edges are needed to shift out the eight leading
zeros and 16 data bits. Extra clock pulses occurring
after the conversion result has been clocked out, and
prior to the rising edge of CS, produce trailing zeros at
DOUT and have no effect on the converter operation.
Force CS high after reading the conversion’s LSB to
reset the internal registers and place the MAX1162 in
shutdown. For maximum throughput, force CS low
again to initiate the next conversion immediately after
the specified minimum time (t
CSW
).
Note: Forcing CS high in the middle of a conversion
immediately aborts the conversion and places the
MAX1162 in shutdown.
C
DAC
32pF
R
IN
800Ω
HOLD
HOLD
C
SWITCH
3pF
AIN
REF
GND
ZERO
CAPACITIVE DAC
AUTO-ZERO
RAIL
TRACK
TRACK
Figure 5. Equivalent Input Circuit
CS
SCLK
2016
24
1214 86
DOUT
D15 D14 D13
D12 D11 D10 D9 D1 D0D8 D5 D4 D3 D2D7 D6
t
CSH
t
TR
t
DO
t
ACQ
t
CSS
t
CH
t
CL
t
DV
Figure 6. External Timing Diagram
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
______________________________________________________________________________________ 11
Output Coding and
Transfer Function
The data output from the MAX1162 is binary and Figure
8 depicts the nominal transfer function. Code transitions
occur halfway between successive-integer LSB values
(V
REF
= 4.096V and 1LSB = 63µV or 4.096V/65536).
Applications Information
External Reference
The MAX1162 requires an external reference with a
+3.8V and AV
DD
voltage range. Connect the external
reference directly to REF. Bypass REF to AGND (pin 3)
with a 4.7µF capacitor. When not using a low-ESR
bypass capacitor, use a 0.1µF ceramic capacitor in
parallel with the 4.7µF capacitor. Noise on the refer-
ence degrades conversion accuracy.
The input impedance at REF is 40kΩ for DC currents.
During a conversion the external reference at REF must
deliver 100µA of DC load current and have an output
impedance of 10Ω or less.
For optimal performance, buffer the reference through
an op amp and bypass the REF input. Consider the
MAX1162’s equivalent input noise (38µV
RMS
) when
choosing a reference.
Input Buffer
Most applications require an input buffer amplifier to
achieve 16-bit accuracy. If the input signal is multi-
plexed, switch the input channel immediately after acqui-
sition, rather than near the end of or after a conversion
(Figure 9). This allows the maximum time for the input
buffer amplifier to respond to a large step change in the
input signal. The input amplifier must have a slew rate of
at least 2V/µs to complete the required output-voltage
change before the beginning of the acquisition time.
At the beginning of the acquisition, the internal sampling
capacitor array connects to AIN (the amplifier output),
causing some output disturbance. Ensure that the sampled
voltage has settled before the end of the acquisition time.
Digital Noise
Digital noise can couple to AIN and REF. The conver-
sion clock (SCLK) and other digital signals active dur-
ing input acquisition contribute noise to the conversion
result. Noise signals synchronous with the sampling
interval result in an effective input offset. Asynchronous
signals produce random noise on the input, whose
high-frequency components can be aliased into the fre-
COMPLETE CONVERSION SEQUENCE
CONVERSION 0
CONVERSION 1
POWERED UPPOWERED UP POWERED DOWN
DOUT
CS
TIMING NOT TO SCALE.
Figure 7. Shutdown Sequence
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000
123
0
FS
FS - 3/2LSB
FS = V
REF
INPUT VOLTAGE (LSB)
1LSB =
V
REF
65536
Figure 8. Unipolar Transfer Function, Full Scale (FS) = V
REF
,
Zero Scale (ZS) = GND
MAX1162
16-Bit, +5V, 200ksps ADC with 10µA
Shutdown
12 ______________________________________________________________________________________
quency band of interest. Minimize noise by presenting
a low impedance (at the frequencies contained in the
noise signal) at the inputs. This requires bypassing AIN
to AGND, or buffering the input with an amplifier that
has a small-signal bandwidth of several MHz, or prefer-
ably both. AIN has 4MHz (typ) of bandwidth.
Distortion
Avoid degrading dynamic performance by choosing an
amplifier with distortion much less than the MAX1162’s
total harmonic distortion (THD = -102dB at 1kHz) at fre-
quencies of interest. If the chosen amplifier has insuffi-
cient common-mode rejection, which results in degraded
THD performance, use the inverting configuration (posi-
tive input grounded) to eliminate errors from this source.
Low temperature-coefficient, gain-setting resistors reduce
linearity errors caused by resistance changes due to self-
heating. To reduce linearity errors due to finite amplifier
gain, use amplifier circuits with sufficient loop gain at the
frequencies of interest.
DC Accuracy
To improve DC accuracy, choose a buffer with an offset
much less than the MAX1162’s offset (1mV (max) for +5V
supply), or whose offset can be trimmed while maintain-
ing stability over the required temperature range.
Serial Interfaces
The MAX1162’s interface is fully compatible with SPI,
QSPI, and MICROWIRE standard serial interfaces.
If a serial interface is available, establish the CPU’s ser-
ial interface as master, so that the CPU generates the
serial clock for the MAX1162. Select a clock frequency
between 100kHz and 4.8MHz:
1) Use a general-purpose I/O line on the CPU to pull
CS low.
2) Activate SCLK for a minimum of 24 clock cycles.
The serial data stream of eight leading zeros fol-
lowed by the MSB of the conversion result begins at
the falling edge of CS. DOUT transitions on SCLK’s
falling edge and the output is available in MSB-first
A0
A1
CLK
CHANGE MUX INPUT HERE
CONVERSION
IN1
A0 A1
IN2
IN3
IN4
OUT
ACQUISITION
4-TO-1
MUX
AIN
CS
MAX1162
CS
TIMING NOT TO SCALE.
Figure 9. Change Multiplexer Input Near Beginning of Conversion to Allow Time for Slewing and Settling
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

MAX1162BEUB+T

Mfr. #:
Buy MAX1162BEUB+T
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 16-Bit 200ksps 4.096V Precision ADC
Lifecycle:
New from this manufacturer.
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