AD8134 Data Sheet
Rev. B | Page 18 of 20
–OUT R
+OUT R
–OUT G
+OUT G
–OUT B
+OUT B
V
OCM
WEIGHTING EQUATIONS:
RED V
OCM
=
K
(V
SYNC
– H
SYNC
) + V
MIDSUPPLY
GREEN V
OCM
=
K
(–2V
SYNC
) + V
MIDSUPPLY
BLUE V
OCM
=
K
(V
SYNC
+ H
SYNC
) + V
MIDSUPPLY
+IN R
–IN R
V
SYNC
H
SYNC
SYNC LEVEL
+IN G
–IN G
+IN B
–IN B
R
1.5k
1.5k
AD8134
750
750
G
1.5k
1.5k
750
750
V
OCM
V
OCM
V
OCM
B
1.5k
1.5k
750
750
OPD
×2
04770-003
2
2
2
Figure 34. AD8134 Sync-On-Common-Mode Encoding Scheme
0
0.5
1.0
1.5
2.0
4.0
3.5
4.5
2.5
3.0
5.0
0.98 0.99 1.00 1.01 1.03
1.04 1.051.02 1.06 1.07
TIME (µs)
H
SYNC
V
SYNC
2.0
2.1
2.2
2.3
2.4
2.9
2.8
3.0
2.5
2.6
2.7
3.1
R
G
B
04770-004
Figure 35. AD8134 Sync-On-Common-Mode Signals in Single 5 V Application
The transmitted common-mode sync signal magnitudes are
scaled by applying a dc voltage to the SYNC LEVEL input,
referenced to the negative supply. The difference between the
voltage applied to the SYNC LEVEL input and the negative
supply sets the peak deviation of the encoded sync signals about
the midsupply common-mode voltage. For example, with the
SYNC LEVEL input set at V
S−
+ 500 mV, the deviation of the
encoded sync pulses about the nominal midsupply common-
mode voltage is typically ±500 mV. The equations in Figure 34
describe how the V
SYNC
and H
SYNC
signals are encoded on each
color’s midsupply common-mode signal. In these equations, the
weights of the V
SYNC
and H
SYNC
signals are ±1 (+1 for high, −1
for low), and the constant K is equal to the peak deviation of the
encoded sync signals.
Figure 35 shows how the sync signals appear on each common-
mode voltage in a single 5 V supply application when the
voltage applied to the SYNC LEVEL input is 500 mV. A typical
setting for the SYNC LEVEL voltage is 500 mV above the
negative supply.
LEVEL-SHIFTING SYNC PULSES ON ±5 V SUPPLIES
The vertical and horizontal sync pulses received from a
computer video port are generally referenced to ground. When
using ±5 V supplies, these pulses must be level-shifted before
being applied to the negative-supply referenced V
SYNC
and H
SYNC
inputs because these inputs are referenced to the negative
supply. The circuit shown in Figure 36 provides the proper sync
pulse level-shifting for a negative supply voltage of −5 V. The
vertical and horizontal sync pulses each require a level-shift
circuit.
6.04k 2.21k
LEVEL-SHIFTED
SYNC PULSE
TO AD8134
GROUND-REFERENCED
SYNC PULSE
1k
V
S
2N3906
04770-035
Figure 36. Level-Shifting Sync Pulses on ±5 V Supplies
Data Sheet AD8134
Rev. B | Page 19 of 20
LAYOUT AND POWER SUPPLY DECOUPLING
CONSIDERATIONS
Standard high speed PCB layout practices should be adhered to
when designing with the AD8134. A solid ground plane is
recommended and good wideband power supply decoupling
networks should be placed as close as possible to the supply
pins. Small surface-mount ceramic capacitors are recommended
for these networks, and tantalum capacitors are recommended
for bulk supply decoupling.
AMPLIFIER-TO-AMPLIFIER ISOLATION
The least amount of isolation between the three amplifiers
exists between Amplifier R and Amplifier G. This is therefore
viewed as the worst-case isolation and is what is reflected in the
Specifications tables and Typical Performance Characteristics.
Refer to the basic test circuit in Figure 5 for test conditions.
EXPOSED PADDLE (EP)
The 24-lead LFCSP package has an exposed paddle on the
underside of its body. To achieve the specified thermal resistance,
it must have a good thermal connection to one of the PCB planes.
The exposed paddle must be soldered to a pad on top of the
board that is connected to an inner plane with several thermal
vias.
AD8134 Data Sheet
Rev. B | Page 20 of 20
OUTLINE DIMENSIONS
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.20
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD-8.
06-
11-2012-A
BOTTOM VIEW
TOP VIEW
EXPOSED
PAD
PIN 1
INDIC
A
T
OR
4.10
4.00 SQ
3.90
SEA
TING
PLANE
0.80
0.75
0.70
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDIC
AT
OR
2.20
2.10 SQ
2.00
1
24
7
12
13
18
19
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
Figure 37. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1
Temperature Package Package Description Package Outline
AD8134ACPZ-R2 −40°C to +85°C 24-Lead LFCSP CP-24-10
AD8134ACPZ-REEL −40°C to +85°C 24-Lead LFCSP CP-24-10
AD8134ACPZ-REEL7 −40°C to +85°C 24-Lead LFCSP CP-24-10
1
Z = RoHS Compliant Part.
©20042016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04770-0-3/16(B)

AD8134ACPZ-R2

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Video Amplifiers Triple Diff Driver w sync-on Common-Mode
Lifecycle:
New from this manufacturer.
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