MAX2742ECM+D

MAX2742
Single-Chip Global Positioning System
Receiver Front-End
4 _______________________________________________________________________________________
Typical Operating Characteristics
(MAX2742 EV kit, V
DD
= +3V, and T
A
= +25°C, unless otherwise noted.)
SUPPLY CURRENT
vs. TEMPERATURE
MAX2742 toc01
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
6040200-20
12
13
14
16
10
-40 80
15
11
V
CC
= +2.7V
V
CC
= +3.0V
V
CC
= +2.4V
LNA/MIXER GAIN
vs. TEMPERATURE
MAX2742 toc02
TEMPERATURE (°C)
LNA-MIXER GAIN (dB)
21
22
23
24
25
26
27
28
29
30
20
V
CC
= +2.4V
V
CC
= +2.7V
V
CC
= +3.0V
6040200-20-40 80
MAXIMUM IF STAGE GAIN
vs. TEMPERATURE
MAX2742 toc03
TEMPERATURE (°C)
VGA GAIN (dB)
76
77
78
79
80
75
V
CC
= +3.0V
V
CC
= +2.7V
V
CC
= +2.4V
6040200-20-40 80
TOTAL CONVERSION GAIN
vs. TEMPERATURE
MAX2742 toc04
TEMPERATURE (
°
C)
SYSTEM GAIN (dB)
102
103
104
105
100
101
6040200-20-40 80
V
CC
= +3.0V
V
CC
= +2.7V
V
CC
= +2.4V
MAX2742
Single-Chip Global Positioning System
Receiver Front-End
_______________________________________________________________________________________ 5
Pin Description
PIN NAME FUNCTION
1 RBIAS
External Bias Resistor. Connect a 100kΩ ±1% resistor in parallel with a 0.1µF capacitor in
series with a 71kΩ resistor to GND.
2 CBIAS External Bias Capacitor. Connect a 0.1µF capacitor to GND.
3, 4, 12, 17, 23,
25, 32, 39, 44, 46
V
DD
Supply Voltage. Bypass to GND with 100pF and 100nF capacitors as close to the pin as
possible with the smaller value capacitor closer to the pin.
5, 6, 8, 9, 13, 24,
30, 38, 42, 45
GND Ground. Connect to PC board ground plane.
7 RFIN LNA Input. Requires external matching network.
10 IFSEL
IF Output Select. Selects output type. Drive high for single-ended output, drive low for
differential output.
11, 21, 22,
27, 33–36, 40
I.C. Internally Connected. Leave unconnected.
14 DCLK Digital Control Clock
15 CLKENB2 Clock Output Enable 2. Drive high to enable limited-swing clock output.
16 CLKENB1 Clock Output Enable 1. Drive high to enable full-swing clock output.
18 AGCFLT AGC External Filter
19, 20
OUT-, OUT+
Differential Comparator Outputs
26 CLKOUT1 Full-Swing Clock Output
28 DOUT Digital Output
29 CLKOUT2 Limited-Swing Clock Output
31 DIN Digital-Control Data Input
37 SHDN
Shutdown. Drive SHDN low to disable all device functions. Drive SHDN high for normal
operation.
41 VTUNE VCO Tuning Input. Connect directly to the loop filter output.
43 CPOUT Charge-Pump Output. Connect directly to the loop filter input.
47, 48
XTALIN1,
XTALIN2
Crystal Oscillator Input. Connect XTALIN1 and XTALIN2 together and to the TCXO output
through a coupling capacitor.
—EP
Exposed Paddle. Internally connected to GND. Connect to PC board ground plane for
optimal performance.
MAX2742
Single-Chip Global Positioning System
Receiver Front-End
6 _______________________________________________________________________________________
Detailed Description
LNA/Mixer
The RF input from the GPS antenna is fed through an
LNA with a 24dB gain. The amplified signal is then fed
to a mixer that downconverts the signal (1575.42MHz)
to a quadrature differential IF of 1.023MHz.
IF Stage
The quadrature IF signals pass through the IF filter,
which rejects the out-of-band spurs by more than 60dB
and the image noise by 18dB (typ). After the image
reject filter, the signal is converted from quadrature to
differential. The filtered IF signal is then amplified by the
AGC block, which sets the VGA output signal level to a
predetermined value through the application using 50dB
of dynamic range. The internal offset-cancellation mech-
anism generates a highpass characteristic for the IF
section with a 1dB corner frequency of about 100kHz.
IF Output Selection
The sampled outputs of the GPS signal are available in
a single-ended or differential format. The IFSEL pin
controls the output format.
Synthesizer
An on-chip VCO provides quadrature differential LO
signals to the downconverting mixer and controls the
frequency. An on-board TCXO generates the reference
frequency. The integrated synthesizer includes the
VCO, TCXO buffer, main frequency divider, phase-fre-
quency detector, and charge pump. It uses an off-chip
PLL loop filter and TCXO. Connect the output of the
TCXO to XTALIN1 and XTALIN2 through a coupling
capacitor.
The main division ratio for the synthesizer is 684. With this
division ratio, a low-side injection LO can be synthesized
with an 18.414MHz TXCO.
Applications Information
Layout Issues
A properly designed PC board is an essential part of any
RF/microwave circuit. On all high-frequency inputs and
outputs, use controlled impedance lines and keep them
as short as possible to minimize losses and radiation.
Keeping the traces short also reduces parasitic induc-
tance. To further reduce the parasitic inductance, use
wider traces and a solid ground or power plane below
the signal traces. Also, place decoupling capacitors as
close to the supply pins as possible. For proper power
dissipation and operation, connect the metal exposed
paddle solidly to the ground plane of the PC board.

MAX2742ECM+D

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
RF Receiver GPS Front End Downconverter
Lifecycle:
New from this manufacturer.
Delivery:
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