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MAX803SQ293T1G

P1-P3P4-P6P7-P9P10-P10
MAX803 Series, NCP803 Series
www.onsemi.com
4
−40°C
−40°C
TYPICAL OPERATING CHARACTERISTICS
0.5
0.4
0.3
0.2
0.1
0
0.5 1.5 2.5 3.5 4.5 6.5
−50 −25 0 25 50 75
SUPPLY VOLTAGE (V)
TEMPERATURE (°C)
Figure 3. Supply Current vs. Supply Voltage
0.5
0.4
0.3
0.2
0.1
0
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
0.6
0.7
85°C
25°C
−40°C
0.5 1.5 2.5 3.5 4.5 6.5
85°C
25°C
V
TH
= 4.63 V
0.3
0.2
0.1
0
0.5 1.5 2.5 3.5 4.5 6.5
SUPPLY VOLTAGE (V)
0.4
85°C
25°C
SUPPLY CURRENT (mA)
V
TH
= 2.93 V
NORMALIZED THRESHOLD VOLTAGE
0.994
0.995
0.996
0.997
0.998
0.999
1.000
1.002
100 125
V
TH
= 1.2 V
−50 −25 0 25 50
0
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
0.1
0.2
0.3
0.4
0.5
75 100
V
CC
= 1.0 V
V
CC
= 3.3 V
V
CC
= 5.0 V
V
TH
= 4.63 V
V
TH
= 1.2 V
0.5 1.0 1.5 2.0 2.5 3.0 3.5
0
SUPPLY VOLTAGE (V)
OUTPUT VOLTAGE V
CC
(mV)
20
40
60
80
100
5.0
Figure 4. Supply Current vs. Supply Voltage
Figure 5. Supply Current vs. Supply Voltage Figure 6. Normalized Reset Threshold Voltage
vs. Temperature
Figure 7. Supply Current vs. Temperature Figure 8. Output Voltage Low vs. Supply
Voltage
5.5 5.5
5.5
1.001
4.0 4.5
85°C
25°C
−40°C
V
TH
= 4.63 V
I
SINK
= 500 mA
RESET ASSERTED
MAX803 Series, NCP803 Series
www.onsemi.com
5
TYPICAL OPERATING CHARACTERISTICS
75
50
25
0
−50 −25 0 25 50 125
TEMPERATURE (°C)
Figure 9. Power−Down Reset Delay vs.
Temperature and Overdrive (V
TH
= 1.2 V)
300
240
180
120
60
0
TEMPERATURE (°C)
POWER−DOWN RESET DELAY (msec)
POWER−DOWN RESET DELAY (msec)
100
125
−50 −25 0 25 50 125
1.1
0.9
0.8
0.7
−50 −25 0 25 50 100
TEMPERATURE (°C)
1.3
NORMALIZED POWER−UP RESET TIMEOUT
V
OD
= V
CC
−V
TH
Figure 10. Power−Down Reset Delay vs.
Temperature and Overdrive (V
TH
= 4.63 V)
Figure 11. Normalized Power−Up Reset vs.
Temperature
75 75
75
100
V
OD
= 10 mV
V
OD
= 20 mV
V
OD
= 100 mV
V
OD
= 200 mV
V
OD
= V
CC
−V
TH
V
OD
= 10 mV
V
OD
= 20 mV
V
OD
= 100 mV
V
OD
= 200 mV
1.0
1.2
100
MAX803 Series, NCP803 Series
www.onsemi.com
6
Detail Operation Description
The MAX803, NCP803 series microprocessor reset
supervisory circuits are designed to monitor the power
supplies in digital systems and provide a reset signal to the
processor without any external components. Figure 2 shows
the timing diagram and a typical application below. Initially
consider that input voltage V
CC
is at a nominal level greater
than the voltage detector upper threshold (
V
TH
). And the
RESE
T
(RESET) output voltage (Pin 2) will be in the high
state for MAX803 and NCP803 devices. If there is an input
power interruption and V
CC
becomes significantly
deficient, it will fall below the lower detector threshold
(V
TH−
). This event causes the RESET output to be in the low
state for the MAX803 and NCP803 devices. After
completion of the power interruption, V
CC
will rise to its
nominal level and become greater than the V
TH
. This
sequence activates the internal oscillator circuitry and
digital counter to count. After the count of the timeout
period, the reset output will revert back to the original state.
t
RP
V
CC
V
TH+
V
TH–
V
CC
V
TH–
0V
V
CC
V
TH–
0V
Input Voltage
Reset Output
MAX803, NCP803
Reset Output
MAX810
Figure 12. Timing Waveforms
P1-P3P4-P6P7-P9P10-P10

MAX803SQ293T1G

Mfr. #:
Buy MAX803SQ293T1G
Manufacturer:
ON Semiconductor
Description:
Supervisory Circuits ANA 2.93V MC RESET
Lifecycle:
New from this manufacturer.
Delivery:
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