74HC74DR2G

© Semiconductor Components Industries, LLC, 2007
February, 2007 Rev. 0
1 Publication Order Number:
74HC74/D
74HC74
Dual D Flip−Flop with Set
and Reset
HighPerformance SiliconGate CMOS
The 74HC74 is identical in pinout to the LS74. The device inputs are
compatible with standard CMOS outputs; with pullup resistors, they
are compatible with LSTTL outputs.
This device consists of two D flipflops with individual Set, Reset,
and Clock inputs. Information at a Dinput is transferred to the
corresponding Q output on the next positive going edge of the clock
input. Both Q and Q outputs are available from each flipflop. The Set
and Reset inputs are asynchronous.
Features
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0 mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the JEDEC Standard No. 7A Requirements
ESD Performance: HBM > 2000 V; Machine Model > 200 V
Chip Complexity: 128 FETs or 32 Equivalent Gates
PbFree Packages are Available
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MARKING
DIAGRAMS
HC74 = Device Code
A = Assembly Location
L, WL = Wafer Lot
Y = Year
W, WW = Work Week
G or G = PbFree Package
TSSOP14
DT SUFFIX
CASE 948G
14
1
SOIC14
D SUFFIX
CASE 751A
14
1
HC74G
AWLYWW
1
14
HC
74
ALYW G
G
1
14
See detailed ordering and shipping information in the package
dimensions section on page 4 of this data sheet.
ORDERING INFORMATION
(Note: Microdot may be in either location)
74HC74
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2
RESET 1
DATA 1
CLOCK 1
SET 1
RESET 2
DATA 2
CLOCK 2
SET 2
1
2
3
4
13
12
11
10
5
6
9
8
Q1
Q1
Q2
Q2
PIN 14 = V
CC
PIN 7 = GND
FUNCTION TABLE
Inputs Outputs
Set Reset Clock Data Q Q
LH XX HL
HL XX LH
L L X X H* H*
HH H HL
HH L LH
H H L X No Change
H H H X No Change
H H X No Change
*Both outputs will remain high as long as Set and Reset are low, but the output
states are unpredictable if Set and Reset go high simultaneously.
LOGIC DIAGRAMPIN ASSIGNMENT
SET 1
CLOCK 1
DATA 1
RESET 1
11
12
13
14
8
9
105
4
3
2
1
7
6
SET 2
CLOCK 2
DATA 2
RESET 2
V
CC
Q2
Q2
GND
Q1
Q1
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ±20 mA
I
out
DC Output Current, per Pin ±25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ±50 mA
P
D
Power Dissipation in Still Air, SOIC Package†
TSSOP Package†
500
450
mW
T
stg
Storage Temperature – 65 to + 150
_C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or TSSOP Package) 260
300
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package: 6.1 mW/_C from 65_ to 125_C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types – 55 + 125
_C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figures 1, 2, 3) V
CC
= 3.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
0
1000
600
500
400
ns
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
74HC74
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3
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Symbol Parameter Test Conditions
V
CC
(V)
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C v 125_C
V
IH
Minimum HighLevel Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
1.5
2.1
3.15
4.2
V
V
IL
Maximum LowLevel Input
Voltage
V
out
= 0.1 V or V
CC
– 0.1 V
|I
out
| v 20 mA
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
OH
Minimum HighLevel Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
V
OL
Maximum LowLevel Output
Voltage
V
in
= V
IH
or V
IL
|I
out
| v 20 mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| v 2.4 mA
|I
out
| v 4.0 mA
|I
out
| v 5.2 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0 mA
6.0 2.0 20 80
mA
NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor HighSpeed CMOS Data Book
(DL129/D).
AC ELECTRICAL CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6.0 ns)
Symbol Parameter
V
CC
(V)
Guaranteed Limit
Unit
– 55 to
25_C
v 85_C v 125_C
f
max
Maximum Clock Frequency (50% Duty Cycle)
(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.8
10
24
28
4.0
8.0
20
24
MHz
t
PLH
,
t
PHL
Maximum Propagation Delay, Clock to Q or Q
(Figures 1 and 4)
2.0
3.0
4.5
6.0
100
75
20
17
125
90
25
21
150
120
30
26
ns
t
PLH
,
t
PHL
Maximum Propagation Delay, Set or Reset to Q or Q
(Figures 2 and 4)
2.0
3.0
4.5
6.0
105
80
21
18
130
95
26
22
160
130
32
27
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
30
15
13
95
40
19
16
110
55
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the ON
Semiconductor HighSpeed CMOS Data Book (DL129/D).
C
PD
Power Dissipation Capacitance (Per FlipFlop)*
Typical @ 25°C, V
CC
= 5.0 V
pF
32
* Used to determine the noload dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
. For load considerations, see Chapter 2 of the
ON Semiconductor HighSpeed CMOS Data Book (DL129/D).

74HC74DR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC FF D-TYPE DUAL 1BIT 14SOIC
Lifecycle:
New from this manufacturer.
Delivery:
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