ADuM5200/ADuM5201/ADuM5202 Data Sheet
Rev. B | Page 22 of 28
For each output channel with C
L
greater than 15 pF, the additional
capacitive supply current is given by
I
AOD
= 0.5 × 10
−3
× ((C
L
− 15) × V
ISO
) × (2f − f
r
); f > 0.5 f
r
(3)
where:
C
L
is the output load capacitance (pF).
V
ISO
is the output supply voltage (V).
f is the input logic signal frequency (MHz); it is half of the input
data rate expressed in units of Mbps.
f
r
is the input channel refresh rate (Mbps).
CURRENT LIMIT AND THERMAL OVERLOAD
PROTECTION
The ADuM5200/ADuM5201/ADuM5202 are protected against
damage due to excessive power dissipation by thermal overload
protection circuits. Thermal overload protection limits the
junction temperature to a maximum of 150°C (typical). Under
extreme conditions (that is, high ambient temperature and
power dissipation), when the junction temperature starts to rise
above 150°C, the PWM is turned off, reducing the output
current to zero. When the junction temperature drops below
130°C (typical), the PWM turns on again, restoring the output
current to its nominal value.
Consider the case where a hard short from V
ISO
to ground occurs.
At first, the ADuM5200/ADuM5201/ADuM5202 reach their
maximum current, which is proportional to the voltage applied
at V
DD1
. Power dissipates on the primary side of the converter
(see Figure 12). If self-heating of the junction becomes great
enough to cause its temperature to rise above 150°C, thermal
shutdown activates, turning off the PWM, and reducing the
output current to zero. As the junction temperature cools and
drops below 130°C, the PWM turns on, and power dissipates
again on the primary side of the converter, causing the junction
temperature to rise to 150°C again. This thermal oscillation
between 130°C and 150°C causes the part to cycle on and off as
long as the short remains at the output.
Thermal limit protections are intended to protect the device
against accidental overload conditions. For reliable operation,
externally limit device power dissipation to prevent junction
temperatures from exceeding 130°C.
POWER CONSIDERATIONS
The ADuM5200/ADuM5201/ADuM5202 power input, data
input channels on the primary side and data input channels on
the secondary side are all protected from premature operation
by UVLO circuitry. Below the minimum operating voltage, the
power converter holds its oscillator inactive and all input channel
drivers and refresh circuits are idle. Outputs remain in a high
impedance state to prevent transmission of undefined states
during power-up and power-down operations.
During application of power to V
DD1
, the primary side circuitry
is held idle until the UVLO preset voltage is reached. At that
time, the data channels initialize to their default low output
state until they receive data pulses from the secondary side.
When the primary side is above the UVLO threshold, the data
input channels sample their inputs and begin sending encoded
pulses to the inactive secondary output channels. The outputs
on the primary side remain in their default low state because
no data comes from the secondary side inputs until secondary
power is established. The primary side oscillator also begins to
operate, transferring power to the secondary power circuits.
The secondary V
ISO
voltage is below its UVLO limit at this point;
the regulation control signal from the secondary is not being
generated. The primary side power oscillator is allowed to free run
in this circumstance, supplying the maximum amount of power to
the secondary, until the secondary voltage rises to its regulation
setpoint. This creates a large inrush current transient at V
DD1
.
When the regulation point is reached, the regulation control
circuit produces the regulation control signal that modulates
the oscillator on the primary side. The V
DD1
current is reduced
and is then proportional to the load current. The inrush current
is less than the short-circuit current shown in Figure 12. The
duration of the inrush current depends on the V
ISO
loading
conditions and the current available at the V
DD1
pin.
As the secondary side converter begins to accept power from
the primary, the V
ISO
voltage starts to rise. When the secondary
side UVLO is reached, the secondary side outputs are initialized
to their default low state until data is received from the correspond-
ing primary side input. It can take up to 1 μs after the secondary
side is initialized for the state of the output to correlate with the
primary side input.
Secondary side inputs sample their state and transmit it to the
primary side. Outputs are valid about 1 μs after the secondary
side becomes active.
Because the rate of charge of the secondary side power supply
is dependent on loading conditions and the input voltage level
and the output voltage level selected, take care with the design
to allow the converter sufficient time to stabilize before valid
data is required.
When power is removed from V
DD1
, the primary side converter and
coupler shut down when the UVLO level is reached. The secondary
side stops receiving power and starts to discharge. The outputs on
the secondary side hold the last state that they received from the
primary side. Either the UVLO level is reached and the outputs are
placed in their high impedance state, or the outputs detect a lack of
activity from the primary side inputs and the outputs are set to
their default low value before the secondary power reaches UVLO.
