ADT7483A
http://onsemi.com
14
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a
start condition, defined as a high-to-low transition
on the serial data line (SDATA), while the serial
clock line (SCLK) remains high. This indicates
that an address/data stream follows. All slave
peripherals connected to the serial bus respond to
the start condition and shift in the next eight bits,
consisting of a 7-bit address (MSB first) plus an
R/W
bit, which determines the direction of the
data transfer, that is, whether data will be written
to, or read from, the slave device. The peripheral
whose address corresponds to the transmitted
address responds by pulling the data line low
during the low period before the ninth clock pulse,
known as the acknowledge bit. All other devices
on the bus now remain idle while the selected
device waits for data to be read from or written to
it. If the R/W
bit is a 0, the master writes to the
slave device. If the R/W
bit is a 1, the master reads
from the slave device.
2. Data is sent over the serial bus in a sequence of
nine clock pulses, eight bits of data followed by an
acknowledge bit from the slave device. Transitions
on the data line must occur during the low period
of the clock signal and remain stable during the
high period, since a low-to-high transition when
the clock is high may be interpreted as a stop
signal. The number of data bytes that can be
transmitted over the serial bus in a single read or
write operation is limited only by what the master
and slave devices can handle.
3. When all data bytes have been read or written,
stop conditions are established. In write mode, the
master will pull the data line high during the tenth
clock pulse to assert a stop condition. In read
mode, the master device will override the
acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse.
This is known as no acknowledge. The master will
then take the data line low during the low period
before the tenth clock pulse, then high during the
tenth clock pulse to assert a stop condition.
Any number of bytes of data may be transferred over the
serial bus in one operation, but it is not possible to mix read
and write in one operation because the type of operation is
determined at the beginning and cannot subsequently be
changed without starting a new operation. For the
ADT7483A, write operations contain either one or two
bytes, while read operations contain one byte.
To write data to one of the device data registers, or to read
data from it, the address pointer register must be set so that
the correct data register is addressed. The first byte of a write
operation always contains a valid address that is stored in the
address pointer register. If data is to be written to the device,
the write operation contains a second data byte that is written
to the register selected by the address pointer register (see
Figure 15).
The device address is sent over the bus followed by R/W
set to 0. This is followed by two data bytes. The first data
byte is the address of the internal data register to be written
to, which is stored in the address pointer register. The second
data byte is the data to be written to the internal data register.
Figure 15. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
1
SCLK
SDATA
00
1
1
0
1
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7483A
START BY
MASTER
19
1
ACK. BY
ADT7483A
9
D7 D6 D5 D4 D3 D2 D1 D0
ACK. BY
ADT7483A
STOP BY
MASTER
1
9
SCLK (CONTINUED)
SDATA (CONTINUED)
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
FRAME 3
DATA BYTE
R/W
