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A1324LLHLT-T

P1-P3P4-P6P7-P9P10-P12
Linear Hall Effect Sensor ICs with Analog Output
A1324, A1325,
and A1326
7
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Typical Characteristics
(30 pieces, 3 fabrication lots)
4
5
6
7
8
9
10
11
12
I
CCav (mA)
Average Supply Current versus Ambient Temperature
V
CC
= 5 V
Average Postive Linearity versus Ambient Temperature
V
CC
= 5 V
Average Sensitivity Ratiometry versus Ambient TemperatureAverage Quiescent Voltage Output Ratiometry versus Ambient Temperature
Average Negative Linearity versus Ambient Temperature
V
CC
= 5 V
– 40 25 150
T
A
(°C)
– 40 25 150
T
A
(°C)
– 40 25 150
T
A
(°C)
– 40 25 150
T
A
(°C)
– 40 25 150
T
A
(°C)
95
96
97
98
99
100
101
102
103
104
105
Lin+
av
(%)
95
96
97
98
99
100
101
102
103
104
105
Lin–
av
(%)
Rat
Sens(
av)
(%)
99.0
99.2
99.4
99.6
99.8
100.0
100.2
100.4
100.6
100.8
101.0
98.0
98.5
99.0
99.5
100.0
100.5
101.0
101.5
102.0
Rat
VOUTQ(
av)
(%)
5.5 to 5.0 V
V
CC
4.5 to 5.0 V
5.5 to 5.0 V
V
CC
4.5 to 5.0 V
Linear Hall Effect Sensor ICs with Analog Output
A1324, A1325,
and A1326
8
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Typical Characteristics, continued
(30 pieces, 3 fabrication lots)
– 40 25 150
T
A
(°C)
– 40 25 150
T
A
(°C)
– 40 25 150
T
A
(°C)
– 40 25 150
T
A
(°C)
2.425
2.445
2.465
2.485
2.505
2.525
2.545
2.565
∆
V
OUT(Q)av
(G)
V
OUT(Q)
(V)
V
OUT(Q)av
(V)
2.0
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Sens
av
(mV/G)
Sens
av
(mV/G)
2.0
2.5
1.0
1.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
∆Sens
av
(%)
-10
-8
-6
-4
-2
0
2
4
6
8
10
-10
-8
-6
-4
-2
0
2
4
6
8
10
4.5 5
V
CC
(V)
5.5
4.5 5
V
CC
(V)
5.5
Average Absolute Quiescent Voltage Output versus Ambient Temperature
V
CC
= 5 V
Quiescent Voltage Output versus Supply Voltage
T
A
= 25°C
Average Sensitivity versus Supply Voltage
T
A
= 25°C
Average Absolute Sensitivity versus Ambient Temperature
V
CC
= 5 V
Average Quiescent Voltage Output Drift versus Ambient Temperature
∆V
OUT(Q)av
values relative to 25°C, V
CC
= 5 V
Average Sensitivity Drift versus Ambient Temperature
∆Sens
av
values relative to 25°C, V
CC
= 5 V
A1324
A1325
A1326
A1324
A1325
A1326
A1324
A1325
A1326
A1324
A1325
A1326
Linear Hall Effect Sensor ICs with Analog Output
A1324, A1325,
and A1326
9
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Amp
Regulator
Clock/Logic
Hall Element
Tuned
Filter
Anti-Aliasing
LP Filter
Concept of Chopper Stabilization Technique
Typical Application Circuit
Chopper Stabilization Technique
When using Hall-effect technology, a limiting factor for
switchpoint accuracy is the small signal voltage developed across
the Hall element. This voltage is disproportionally small relative
to the offset that can be produced at the output of the Hall IC.
This makes it difficult to process the signal while maintaining an
accurate, reliable output over the specified operating temperature
and voltage ranges. Chopper stabilization is a unique approach
used to minimize Hall offset on the chip. Allegro employs a
technique to remove key sources of the output drift induced by
thermal and mechanical stresses. This offset reduction technique
is based on a signal modulation-demodulation process. The
undesired offset signal is separated from the magnetic field-
induced signal in the frequency domain, through modulation.
The subsequent demodulation acts as a modulation process for
the offset, causing the magnetic field-induced signal to recover
its original spectrum at baseband, while the DC offset becomes
a high-frequency signal. The magnetic-sourced signal then can
pass through a low-pass filter, while the modulated DC offset is
suppressed. In addition to the removal of the thermal and stress
related offset, this novel technique also reduces the amount of
thermal noise in the Hall IC while completely removing the
modulated residue resulting from the chopper operation. The
chopper stabilization technique uses a high frequency sampling
clock. For demodulation process, a sample-and-hold technique
is used. This high-frequency operation allows a greater sampling
rate, which results in higher accuracy and faster signal-processing
capability. This approach desensitizes the chip to the effects
of thermal and mechanical stresses, and produces devices that
have extremely stable quiescent Hall output voltages and precise
recoverability after temperature cycling. This technique is made
possible through the use of a BiCMOS process, which allows the
use of low-offset, low-noise amplifiers in combination with high-
density logic integration and sample-and-hold circuits.
GND
1[1]
3[2]
Pin numbers in brackets
refer to the UA package
2[3]
VOUT
V
OUT
A132x
VCC
V+
0.1 µF
C
BYPASS
P1-P3P4-P6P7-P9P10-P12

A1324LLHLT-T

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Description:
SENSOR HALL EFFECT ANALOG SOT23W
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