VIPER100A Datasheet VIPER100A, VIPER100(022Y), VIPER100A(022Y) | P13-P15

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Operation Description:

Current Mode Topology:

The current mode control method, like the one integrated in the VIPer100/100A, uses two control loops -

an inner current control loop and an outer loop for voltage control. When the Power MOSFET output

transistor is on, the inductor current (primary side of the transformer) is monitored with a SenseFET

technique and converted into a voltage V

proportional to this current. When V

reaches V

COMP

(the

amplified output voltage error) the power switch is switched off. Thus, the outer voltage control loop

defines the level at which the inner loop regulates peak current through the power switch and the primary

winding of the transformer.

Excellent open loop D.C. and dynamic line regulation is ensured due to the inherent input voltage

feedforward characteristic of the current mode control. This results in improved line regulation,

instantaneous correction to line changes, and better stability for the voltage regulation loop.

Current mode topology also ensures good limitation in case there is a short circuit. During the first phase

the output current increases slowly following the dynamic of the regulation loop. Then it reaches the

maximum limitation current internally set and finally stops because the power supply on V

is no longer

correct. For specific applications the maximum peak current internally set can be overridden by externally

limiting the voltage excursion on the COMP pin. An integrated blanking filter inhibits the PWM comparator

output for a short time after the integrated Power MOSFET is switched on. This function prevents

anomalous or premature termination of the switching pulse in case there are current spikes caused by

primary side capacitance or secondary side rectifier reverse recovery time.

Stand-by Mode

Stand-by operation in nearly open load conditions automatically leads to a burst mode operation allowing

voltage regulation on the secondary side. The transition from normal operation to burst mode operation

happens for a power P

STBY

given by :

Where:

is the primary inductance of the transformer. F

is the normal switching frequency.

STBY

is the minimum controllable current, corresponding to the minimum on time that the device is able

to provide in normal operation. This current can be computed as :

+ t

is the sum of the blanking time and of the propagation time of the internal current sense and

comparator, and represents roughly the minimum on time of the device. Note: that PSTBY may be

affected by the efficiency of the converter at low load, and must include the power drawn on the primary

auxiliary voltage.

As soon as the power goes below this limit, the auxiliary secondary voltage starts to increase above the

13V regulation level, forcing the output voltage of the transconductance amplifier to low state (V

COMP

COMPth

). This situation leads to the shutdown mode where the power switch is maintained in the Off

state, resulting in missing cycles and zero duty cycle. As soon as V

gets back to the regulation level

and the V

COMPth

threshold is reached, the device operates again. The above cycle repeats indefinitely,

providing a burst mode of which the effective duty cycle is much lower than the minimum one when in

normal operation. The equivalent switching frequency is also lower than the normal one, leading to a

reduced consumption on the input main supply lines. This mode of operation allows the VIPer100/100A

to meet the new German "Blue Angel" Norm with less than 1W total power consumption for the system

when working in stand-by mode. The output voltage remains regulated around the normal level, with a

low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the

output capacitors and low output current drawn in such conditions.The normal operation resumes

automatically when the power gets back to higher levels than P

STBY

STB Y

---L

STBY

SW=

STB Y

+()V

-----------------------------=

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High Voltage Start-up Current Suorce

An integrated high voltage current source provides a bias current from the DRAIN pin during the start-up

phase. This current is partially absorbed by internal control circuits which are placed into a standby mode

with reduced consumption and also provided to the external capacitor connected to the V

pin. As soon

as the voltage on this pin reaches the high voltage threshold V

DDon

of the UVLO logic, the device

becomes active mode and starts switching. The start-up current generator is switched off, and the

converter should normally provide the needed current on the V

pin through the auxiliary winding of the

transformer, as shown on (see Figure 18).

In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage

supply current to the V

pin (i.e. short circuit on the output of the converter), the external capacitor

discharges to the low threshold voltage V

DDoff

of the UVLO logic, and the device goes back to the inactive

state where the internal circuits are in standby mode and the start-up current source is activated. The

converter enters a endless start-up cycle, with a start-up duty cycle defined by the ratio of charging

current towards discharging when the VIPer100/100A tries to start. This ratio is fixed by design to 2A to

15A, which gives a 12% start-up duty cycle while the power dissipation at start-up is approximately 0.6W,

for a 230Vrms input voltage.

This low value start-up duty cycle prevents the application of stress to the output rectifiers as well as the

transformer when a short circuit occurs.

The external capacitor C

VDD

on the V

pin must be sized according to the time needed by the converter

to start up, when the device starts switching. This time t

depends on many parameters, among which

transformer design, output capacitors, soft start feature, and compensation network implemented on the

COMP pin. The following formula can be used for defining the minimum capacitor needed:

where:

is the consumption current on the V

pin when switching. Refer to specified I

DD1

and I

2 values.

is the start up time of the converter when the device begins to switch. Worst case is generally at full

load.

DDhyst

is the voltage hysteresis of the UVLO logic (refer to the minimum specified value).

The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also

used as the compensation network. In this case, the regulation loop bandwidth is rather low, because of

the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics

of (see Figure 19) can be used. It mixes a high performance compensation network together with a

separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be

adjusted separately.

If the device is intentionally shut down by tying the COMP pin to ground, the device is also performing

start-up cycles, and the V

voltage is oscillating between V

DDon

and V

DDoff

This voltage can be used for supplying external functions, provided that their consumption does not

exceed 0.5mA. (see Figure 20) page 17 shows a typical application of this function, with a latched

shutdown. Once the "Shutdown" signal has been activated, the device remains in the Off state until the

input voltage is removed.

VDD

DDhyst

-------------------->

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Figure 18. Behaviour of the high voltage current source at start-up

Ref.

UNDERVOLTAGE

LOCK OUT LOGIC

15 mA

1 mA

3 mA

2 mA

15 mA

VDD

DRAIN

SOURC

VIPer100

Auxiliary primary

winding

VDD

DDoff

VDDon

Start up duty cycle ~ 12%

VDD

FC00100

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

VIPER100A

Mfr. #:

Buy VIPER100A

Manufacturer:

STMicroelectronics

Description:

AC/DC Converters 700V 3A SMPS

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