MAX9796EBX+TG45 Datasheet MAX9796EBX+TG45 | P19-P21

MAX9796

2.3W, High-Power Class D Audio Subsystem

with DirectDrive Headphone Amplifiers

______________________________________________________________________________________ 19

C Interface

The MAX9796 features an I

C 2-wire serial interface

consisting of a serial-data line (SDA) and a serial-clock

line (SCL). SDA and SCL facilitate communication

between the MAX9796 and the master at clock rates up

to 400kHz. Figure 7 shows the 2-wire interface timing

diagram. The MAX9796 is a receive-only slave device

relying on the master to generate the SCL signal. The

master, typically a microcontroller, generates SCL and

initiates data transfer on the bus. The MAX9796 cannot

write to the SDA bus except to acknowledge the receipt

of data from the master. The MAX9796 does not

acknowledge a read command from the master.

A master device communicates to the MAX9796 by

transmitting the proper address followed by the data

word. Each transmit sequence is framed by a START (S)

or REPEATED START (Sr) condition and a STOP (P) con-

dition. Each word transmitted over the bus is 8 bits long

and is always followed by an acknowledge clock pulse.

The MAX9796 SDA line operates as both an input and

an open-drain output. A pullup resistor, greater than

500Ω, is required on the SDA bus. The MAX9796 SCL

line operates as an input only. A pullup resistor, greater

than 500Ω, is required on SCL if there are multiple mas-

ters on the bus, or if the master in a single-master sys-

tem has an open-drain SCL output. Series resistors in

line with SDA and SCL are optional. Series resistors

protect the digital inputs of the MAX9796 from high-

voltage spikes on the bus lines, and minimize crosstalk

and undershoot of the bus signals.

Bit Transfer

One data bit is transferred during each SCL cycle. The

data on SDA must remain stable during the high period

of the SCL pulse. Changes in SDA while SCL is high

are control signals (see the

START and STOP

Conditions

section). SDA and SCL idle high when the

C bus is not busy.

START and STOP Conditions

A master device initiates communication by issuing a

START condition. A START condition is a high-to-low

transition on SDA with SCL high. A STOP condition is a

low-to-high transition on SDA while SCL is high (Figure

8). A START condition from the master signals the

beginning of a transmission to the MAX9796. The mas-

ter terminates transmission and frees the bus by issu-

ing a STOP condition. The bus remains active if a

REPEATED START condition is generated instead of a

STOP condition.

SCL

SDA

START

CONDITION

STOP

CONDITION

REPEATED

START

CONDITION

START

CONDITION

HD, STA

SU, STA

HD, STA

BUF

SU, STO

LOW

SU, DAT

HD, DAT

HIGH

Figure 7. 2-Wire Serial-Interface Timing Diagram

SCL

SDA

SSrP

Figure 8. START, STOP, and REPEATED START Conditions

MAX9796

Early STOP Conditions

The MAX9796 recognizes a STOP condition at any point

during data transmission except if the STOP condition

occurs in the same high pulse as a START condition.

Slave Address

The MAX9796 is available with one preset slave

address (see Table 1). The address is defined as the

seven most significant bits (MSBs) followed by the

read/write (R/W) bit. The address is the first byte of

information sent to the MAX9796 after the START condi-

tion. The MAX9796 is a slave device only capable of

being written to. The R/W bit should be a zero when

configuring the MAX9796.

Acknowledge

The acknowledge bit (ACK) is a clocked 9

bit that the

MAX9796 uses to handshake receipt of each byte of

data (see Figure 9). The MAX9796 pulls down SDA dur-

ing the master-generated 9

clock pulse. Monitoring

ACK allows for detection of unsuccessful data transfers.

An unsuccessful data transfer occurs if a receiving

device is busy or if a system fault has occurred. In the

event of an unsuccessful data transfer, the bus master

may reattempt communications.

Write Data Format

A write to the MAX9796 includes transmission of a

START condition, the slave address with the R/W bit set

to 0 (Table 1), one byte of data to configure the

Command Register, and a STOP condition. Figure 10

illustrates the proper format for one frame.

The MAX9796 only accepts write data, but it acknowl-

edges the receipt of the address byte with the R/W bit

set high. The MAX9796 does not write to the SDA bus

in the event that the R/W bit is set high. Subsequently,

the master reads all 1’s from the MAX9796. Always set

the R/W bit to zero to avoid this situation.

Programming the MAX9796

The MAX9796 is programmed through six control regis-

ters. Each register is addressed by the three MSBs

(B5–B7) followed by five configure bits (B0–B4) as

shown in Table 2. Correct programming of the MAX9796

requires writing to all six control registers. Upon power-

on, their default settings are as listed in Table 3.

2.3W, High-Power Class D Audio Subsystem

with DirectDrive Headphone Amplifiers

20 ______________________________________________________________________________________

SCL

START

CONDITION

SDA

289

CLOCK PULSE FOR

ACKNOWLEDGMENT

ACKNOWLEDGE

NOT ACKNOWLEDGE

SLAVE ADDRESS

A6 A5 A4 A3 A2 A1 A0 R/W

10011010

Figure 9. Acknowledge

ACK

ACKNOWLEDGE FROM MAX9796

R/W

ACKNOWLEDGE

FROM MAX9796

B7 B6

B3 B2

COMMAND BYTE IS STORED ON

RECEIPT OF STOP CONDITION

ACK

B1 B0

SLAVE ADDRESS COMMAND BYTE

Figure 10. Write Data Format Example

Table 1. MAX9796 Address Map

B7 B6 B5 B4 B3 B2 B1 B0

FUNCTION

COMMAND DATA

Input Mode Control 0 0 0 INA+20dB INMODE (Tables 5a and 5b)

Mono Volume Control 0 0 1 MVOL (Table 7)

Left Volume Control 0 1 0 LVOL (Table 7)

Right Volume Control 0 1 1 RVOL (Table 7)

Output Mode Control 1 0 0 MONO+6dB OUTMODE (Table 9)

Global Control Register 1 0 1 SHDN IN+6dB MUTE SSM MONO

Table 2. Control Registers

Input Mode Control

The MAX9796 has three flexible inputs that can be con-

figured as single-ended stereo inputs or differential

mono inputs. All input signals are summed into three

unique signals, Left (L), Right (R), and Mono (M), which

are routed to the output amplifiers. The bit B4 allows

the option of boosting low-level signals on INA. B4 can

be set as follows:

1 = Input A’s gain +20dB for low-level signals such as

FM receivers.

0 = Input A’s gain is either 0dB or +6dB as set by

IN+6dB (bit B3 of the Control Register).

Tables 5a and 5b show how the inputs–INA, INB, and

INC–are mixed to create the internal signals left (L),

right (R), and mono (M).

MAX9796

2.3W, High-Power Class D Audio Subsystem

with DirectDrive Headphone Amplifiers

______________________________________________________________________________________ 21

COMMAND DATA DESCRIPTION

Input Mode (000) 10000 Input A gain = +20dB; input A, B, and C singled-ended stereo inputs

Mono Volume (001) 11111 Maximum volume

Left Volume (010) 11111 Maximum volume

Right Volume (011) 11111 Maximum volume

Output Mode (100) 01000 Mode 8: stereo headphone, mono speaker

Global Control Register (101) 00011 Powered-off, input B/C gain = 0dB, MUTE off, SSM on, MONO on

Table 3. Power-On Reset Conditions

B7 B6 B5 B4 B3 B2 B1 B0

Input Mode Control 0 0 0 INA+20dB INMODE (Tables 5a and 5b )

Table 4. Input Mode Control Register

PROGRAMMING MODE INPUT CONFIGURATION

INMODE

B3 B2 B1 B0

INA1 INA2 INB1 INB2 INC1 INC2

0000LRLRLR

0001 L R L R M+ M-

0010 L R M+ M- L R

0 0 1 1 L R M+ M- M+ M-

0 1 0 0 L R R+ R- L+ L-

0 1 0 1 L R L+ L- R+ R-

0110M+ M- L R L R

0 1 1 1 M+ M- L R M+ M-

1 0 0 0 M+ M- M+ M- L R

1 0 0 1 M+ M- M+ M- M+ M-

1 0 1 0 M+ M- R+ R- L+ L-

1 0 1 1 M+ M- L+ L- R+ R-

Table 5a. Input Mode

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MAX9796EBX+TG45

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Maxim Integrated

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IC AMP AUDIO 2.3W MONO D 36UCSP

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