SP690T/S/R JAN 30-06 SP690T/S/R, 802/T/S/R, 804T/S/R, 805T/S/R Low Power Microprocessor Supervisory © 2006 Sipex Corporation
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Figure 24. Interfacing to Microprocessors with
Bidirectional RESET I/O
V
CC
GND
V
CC
GND
RESET
RESET
4.7KΩ
µP
Buffered RESET connects to System Components
Monitoring an Additional Power Supply
These µP supervisors can monitor either positive
or negative supplies using a resistor voltage
divider to PFI. PFO can be used to generate an
interrupt to the µP, as seen in Figure 23.
Interfacing to µPs with Bidirectional
Reset Pins
Any µPs with bidirectional reset pins, such as
the Motorola 68HC11 series, can interface with
the SP690_ and the SP802_ RESET outputs.
For example, if the RESET output is driven
HIGH and the µP wants to pull it LOW,
indeterminate logic levels may result. To correct
this, connect a 4.7kΩ resistor between the
RESET output and the µP reset I/O, as in
Figure 24. Buffer the RESET output to other
system components.
Negative-Going V
CC
Transients
While issuing resets to the µP during power-up,
power-down, and brownout conditions, these
supervisors are relatively immune to short-
duration negative-going V
CC
transients
(glitches). It is usually undesirable to reset the
µP when V
CC
experiences only small glitches.
Figure 25 shows maximum transient duration
vs. reset-comparator overdrive, for which reset
pulses are not generated. The data was generated
using negative-going V
CC
pulses, starting at
3.3V and ending below the reset threshold by
the magnitude indicated (reset comparator
overdrive). The graph shows the maximum pulse
width a negative-going V
CC
transient may
typically have without causing a reset pulse to
be issued. As the amplitude of the transient
increases (i.e. goes farther below the reset
threshold), the maximum allowable pulse width
decreases. Typically, a V
CC
transient that goes
100mV below the reset threshold and lasts for
40µs or less will not cause a reset pulse to be
issued. A 100nF bypass capacitor mounted close
to the V
CC
pin provides additional transient
immunity.
Figure 25. Maximum Transient Duration without
Causing a Reset Pulse vs. Reset Comparator Overdrive
1nF Capacitor
V
OUT
TO GND
Above Line
RESET
Generated
NO
RESET
Generated
