DocID029495 Rev 1 9/20
SRK2001A Operation description
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7 Operation description
The device block diagram is shown in Figure 1 on page 3. The SRK2001A can be supplied
through the VCC pin by the same converter output voltage, within a wide voltage range
(from 4.5 V to 32 V), internally clamped to V
CCZ
(36 V typical). An internal UVLO
(undervoltage lockout) circuit with hysteresis keeps the device switched off at supply voltage
lower than the turn-on level V
CC_On
, with reduced consumption.
After the startup, the operation with V
CC
floating (or disconnected by supply voltage) while
pins DVS1,2 are switching is not allowed: this in order to avoid that a dV/dt on the DVS pin
may cause a high flowing current with possible damage of the IC.
The core of the device is the control logic block, implemented by asynchronous logic: this
digital circuit generates the logic signals to the output drivers, so that the two external power
MOSFETs are switched on and off, depending on the evolution of their drain-source
voltages, sensed on the DVS-SVS pin pairs through the comparators block.
The logic that controls the driving of the two SR MOSFETs is based on two gate-driver state
machines working in parallel in an interlocked way to avoid switching on both gate drivers at
the same time. A third state machine manages the transitions from the normal operation to
the low consumption mode and vice versa.
7.1 Drain voltage sensing
The SRK2001A basic operation is such that each synchronous rectifier MOSFET is
switched on whenever the corresponding transformer half-winding starts conducting (i.e.
when the MOSFET body diode, or an external diode in parallel, starts conducting) and it is
then switched off when the flowing current approaches zero. To understand the polarity and
the level of this current, the IC is provided with two pairs of pins (DVS1-SVS1 and DVS2-
SVS2) that sense the drain-source voltage of either MOSFET (Kelvin sensing). In order to
limit dynamic current injection in any condition, at least 100 resistors in series to DVS1,2
pins must be used.
Referring to the typical waveforms in Figure 5, there are three significant voltage thresholds:
the first one, V
TH_A
(= 1.4 V), sensitive to positive-going edges, arms the opposite gate
driver (interlock function). The second one, V
TH_PT
(= 0.7 V), sensitive to negative-going
edges provides a pre-trigger of the gate driver and sets the internal clock; the third one
V
TH-ON
is the (negative) threshold that triggers the gate driver as the body diode of the SR
MOSFET starts conducting.
