LTC1407/LTC1407A
8
1407fb
CH0
+
(Pin 1): Noninverting Channel 0. CH0
+
operates
fully differentially with respect to CH0
–
with a 0V to 2.5V
differential swing and a 0 to V
DD
absolute input range.
CH0
–
(Pin 2): Inverting Channel 0. CH0
–
operates fully
differentially with respect to CH0
+
with a –2.5V to 0V dif-
ferential swing and a 0 to V
DD
absolute input range.
V
REF
(Pin 3): 2.5V Internal Reference. Bypass to GND and
a solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum in parallel with 0.1µF ceramic). Can be
overdriven by an external reference voltage ≥2.55V and
≤V
DD
.
CH1
+
(Pin 4): Noninverting Channel 1. CH1
+
operates
fully differentially with respect to CH1
–
with a 0V to 2.5V
differential swing and a 0 to V
DD
absolute input range.
CH1
–
(Pin 5): Inverting Channel 1. CH1
–
operates fully
differentially with respect to CH1
+
with a –2.5V to 0V dif-
ferential swing and a 0 to V
DD
absolute input range.
GND (Pins 6, 11): Ground and Exposed Pad. This single
ground pin and the Exposed Pad must be tied directly to
the solid ground plane under the part. Keep in mind that
analog signal currents and digital output signal currents
fl ow through these connections.
V
DD
(Pin 7): 3V Positive Supply. This single power pin
supplies 3V to the entire chip. Bypass to GND pin and
solid analog ground plane with a 10µF ceramic capacitor
(or 10µF tantalum) in parallel with 0.1µF ceramic. Keep in
mind that internal analog currents and digital output signal
currents fl ow through this pin. Care should be taken to
place the 0.1µF bypass capacitor as close to Pins 6 and 7
as possible.
SDO (Pin 8): Three-State Serial Data Output. Each pair of
output data words represent the two analog input channels
at the start of the previous conversion.
SCK (Pin 9): External Clock Input. Advances the conver-
sion process and sequences the output data on the rising
edge. One or more pulses wake from sleep.
CONV (Pin 10): Convert Start. Holds the two analog input
signals and starts the conversion on the rising edge. Two
pulses with SCK in fi xed high or fi xed low state starts Nap
mode. Four or more pulses with SCK in fi xed high or fi xed
low state starts Sleep mode.
PIN FUNCTIONS
BLOCK DIAGRAM
–
+
1
2
7
3
6
S AND H
–
+
4
5
S AND H
GND
11
EXPOSED PAD
V
REF
10µF
CH0
–
CH0
+
CH1
–
CH1
+
3V10µF
LTC1407A
8
10
9
THREE-
STATE
SERIAL
OUTPUT
PORT
MUX
2.5V
REFERENCE
TIMING
LOGIC
V
DD
SDO
CONV
SCK
1407A BD
3Msps
14-BIT ADC
14-BIT LATCH14-BIT LATCH
