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MAX9152ESE+T

P1-P3P4-P6P7-P9P10-P12
Input Fail-Safe
The differential inputs of the MAX9152 do not have
internal fail-safe biasing. If fail-safe biasing is required,
it can be implemented with external large-value resis-
tors. IN_+ should be pulled up to V
CC
with 10kΩ and
IN_ should be pulled down to GND with 10kΩ. The volt-
age-divider formed by the 10kΩ resistors and the 100Ω
termination resistor (across IN_+ and IN_-) provides a
slight positive differential bias and sets a high state at
the device output when inputs are undriven.
Output Resistance
The MAX9152 has a selectable differential output resis-
tance to reduce reflections from impedance discontinu-
ities in the interconnect. Reflections are reduced,
compared to a high-impedance output. A termination
resistor at the receiver is still required and is the primary
termination for the interconnect. Select the output resis-
tance that best matches the differential characteristic
impedance of the interconnect used.
Select Function
The SEL0 and SEL1 logic inputs allow the device to be
configured as a high-speed differential crosspoint, 2:1
mux, 1:2 demux, dual repeater, or 1:2 splitter (Figure
8). See Table 1 for mode selection settings.
Enable Function
The EN0 and EN1 logic inputs enable and disable dri-
ver outputs OUT0 and OUT1. Setting EN0 or EN1 high
enables the corresponding driver output. Setting EN0
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
_______________________________________________________________________________________ 7
1.5V
EN0 = EN1 = HIGH
V
ID
= (V
IN_+
) − (V
IN_-
)
t
HOLD
t
SWITCH
t
SET
V
ID
= 0
V
ID
= 0
IN1 IN0
IN0+
IN0-
IN1-
IN1+
OUT_-
SEL_
OUT_+
1.5V
EN0 = EN1 = HIGH
V
ID
= (V
IN_+
) − (V
IN_-
)
t
HOLD
t
SWITCH
t
SET
V
ID
= 0
V
ID
= 0
IN0 IN1
IN0+
IN0-
IN1-
IN1+
OUT_+
SEL_
OUT_-
Figure 2. Input to Rising Edge Select Setup, Hold, and Mux Switch Timing Diagram
Figure 3. Input to Falling Edge Select Setup, Hold, and Mux Switch Timing Diagram
MAX9152
or EN1 low puts the corresponding driver output into a
high-impedance state (the differential output resistance
also becomes high impedance).
Applications Information
Unused Differential Inputs
Unused differential inputs should be tied to ground and
V
CC
to prevent the high-speed input stage from switch-
ing due to noise. IN_+ should be pulled to V
CC
with
10kΩ and IN_- should be pulled to GND with 10kΩ.
Expanding the Number
of LVDS Output Ports
Devices can be cascaded to make larger switches.
Total propagation delay and total jitter should be con-
sidered to determine the maximum allowable switch
size. Three MAX9152s are needed to make a 2 input x
4 output crosspoint switch with two device propagation
delays. Seven MAX9152s make a 2 input x 8 output
crosspoint with three device delays.
Accepting PECL Inputs
The inputs accept PECL signals with the use of an
attenuation circuit, as shown in Figure 9.
Power-Supply Bypassing
Bypass V
CC
to ground with high-frequency surface-
mount ceramic 0.1µF and 0.001µF capacitors in paral-
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
8 _______________________________________________________________________________________
1/2 MAX9152
3V
1.5V1.5V
EN_
50%
50%
50%
t
PHZ
t
PLZ
t
PZH
t
PZL
50%
0
VOH
1.2V
1.2V
VOL
PULSE
GENERATOR
OUT_+
OUT_-
V
ID
= (V
IN_+
)–(V
IN_-
)
V
OUT_
+ WHEN V
ID
= +100mV
V
OUT_
- WHEN V
ID
= -100mV
V
OUT_
+ WHEN V
ID
= -100mV
V
OUT_
- WHEN V
ID
= +100mV
C
L
R
L
/2
R
L
/2
+1.2V
IN_+
IN_-
EN_
50Ω
C
L
SEL0
SEL1
0
1
0
1
IN1+
IN1-
ENABLED
PULSE
GENERATOR
OUT0+
OUT0-
OUT1+
OUT1-
C
L
R
L
R
L
IN0+
IN0-
50Ω
C
L
50Ω
C
L
C
L
MAX9152
Figure 4. Output Active to High-Z and High-Z to Active Test
Circuit and Timing Diagram
Figure 5. Output Transition Time, Propagation Delay, and Output Channel-to-Channel Skew Test Circuit
SEL0 SEL1 OUT0 OUT1 MODE
L L IN0 IN0 1:2 splitter
L H IN0 IN1 Repeater
H L IN1 IN0 Switch
H H IN1 IN1 1:2 splitter
Table 1. Input/Output Function Table
lel as close to the device as possible, with the smaller
value capacitor closest to V
CC
.
Differential Traces
Trace characteristics affect the performance of the
MAX9152. Use controlled-impedance traces. Eliminate
reflections and ensure that noise couples as common
mode by running the differential trace pairs close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Maintain the distance between the differential traces to
avoid discontinuities in differential impedance. Avoid
90° turns and minimize the number of vias to further
prevent impedance discontinuities.
Cables and Connectors
Transmission media should have nominal differential
impedance of 75Ω or 100Ω. Use cables and connec-
tors that have matched differential impedance to mini-
mize impedance discontinuities.
Avoid the use of unbalanced cables such as ribbon or
simple coaxial cable. Balanced cables such as twisted
pair offer superior signal quality and tend to generate
less EMI due to canceling effects. Balanced cables
tend to pick up noise as common mode, which is
rejected by the differential receiver.
Board Layout
For LVDS applications, a four-layer printed-circuit (PC)
board that provides separate power, ground, and sig-
nal planes is recommended.
MAX9152
800Mbps LVDS/LVPECL-to-LVDS 2 x 2
Crosspoint Switch
_______________________________________________________________________________________ 9
20% 20%
50% 50%
t
PLHD
AND t
PHLD
ARE MEASURED FOR ANY COMBINATION OF SEL0 AND SEL1.
80% 80%
V
ID
= (V
IN_+
) - (V
IN_-
)
V
OD
= (V
OUT_+
) - (V
OUT_-
)
V
OD
= 0
V
OD
= 0 V
OD
= 0
V
ID
= 0 V
ID
= 0
V
OD
= 0
+V
OD
-V
OD
t
LHT
t
HLT
V
OUT_-
V
OUT_+
V
IN_-
V
IN_+
t
PLHD
t
PHLD
Figure 6. Output Transition Time and Propagation Delay Timing
Diagram
t
CCS
IS MEASURED WITH SEL0 = SEL1 = HIGH OR LOW
(1:2 SPLITTER MODE)
V
OD
= (V
OUT_+
) - (V
OUT_-
)
V
OD
= 0 V
OD
= 0
V
OD
= 0
V
OD
= 0
V
OUT1-
V
OUT1+
V
OUT0-
V
OUT0+
t
CCS
t
CCS
Figure 7. Output Channel-to-Channel Skew
OUT0
OUT0 OR OUT1
OUT1
2 x 2 CROSSPOINT
2:1 MUX
1:2 DEMUX
1:2 SPLITTER
DUAL REPEATER
OUT0
OUT1
OUT0
OUT1
OUT0
OUT1
IN0
IN1
IN0
IN1
IN0
IN1
IN0 OR IN1
IN0 OR IN1
Figure 8. Programmable Configurations
P1-P3P4-P6P7-P9P10-P12

MAX9152ESE+T

Mfr. #:
Buy MAX9152ESE+T
Manufacturer:
Maxim Integrated
Description:
Analog & Digital Crosspoint ICs LVDS/LVPECL-to-LVDS 2x2 Crosspoint Swtch
Lifecycle:
New from this manufacturer.
Delivery:
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