MAX9152EUE+ Datasheet MAX9152ESE+, MAX9152EUE+, MAX9152ESE+T | P4-P6

DIFFERENTIAL OUTPUT EYE PATTERN

IN 1:2 SPLITTER MODE AT 800Mbps

CONDITIONS: 3.3V, PRBS = 2

-1 DATA PATTERN,

| = 200mV, V

= +1.2V

HORIZONTAL SCALE = 200ps/div

VERTICAL SCALE = 100mV/div

MAX9152 toc01

150

250

350

450

550

650

50 10075 125 150 175 200

DIFFERENTIAL

OUTPUT VOLTAGE vs. LOAD

MAX9152 toc02

LOAD RESISTOR (Ω)

DIFFERENTIAL OUTPUT VOLTAGE (mV)

NC/RSEL = LOW OR OPEN

NC/RSEL = HIGH

100 300200 400 500 600 700 800

SUPPLY CURRENT vs. DATA RATE

MAX9152 toc03

DATA RATE (Mbps)

SUPPLY CURRENT (mA)

Typical Operating Characteristics

= +3.3V, R

= 100Ω, NC/RSEL = high, C

= 5pF, input transition time = 600ps (20% to 80%), V

= 200mV, PRBS = 2

- 1 data

pattern, V

= +1.2V, T

= +25°C, unless otherwise noted.)

MAX9152

800Mbps LVDS/LVPECL-to-LVDS 2 x 2

Crosspoint Switch

4 _______________________________________________________________________________________

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Pulse Skew |t

PLHD

-t

PHLD

| (Note 6) t

SKEW

Figures 5, 6 25 90 ps

Output Channel-to-Channel Skew t

CCS

Figures 5, 7 20 50 ps

Output Low-to-High Transition

Time (20% to 80%)

LHT

Figures 5, 6 160 270 480 ps

Output High-to-Low Transition

Time (20% to 80%)

HLT

Figures 5, 6 160 270 480 ps

= 200mV, V

= 1.2V, 50% duty

cycle, 800Mbps, input transition time =

600ps (20% to 80%)

10 30

LVDS Data Path Peak-to-Peak

Jitter (Note 7)

JIT

= 200mV, V

= 1.2V, PRBS = 2

- 1

data pattern, 800Mbps, input transition

time = 600ps (20% to 80%)

65 120

AC ELECTRICAL CHARACTERISTICS (continued)

= +3.0V to +3.6V, NC/RSEL = open for R

= 75Ω ±1%, NC/RSEL = high for R

= 100Ω ±1%, C

= 5pF, differential input voltage

| = 0.15V to V

, EN_ = high, SEL0 = low, SEL1 = high, differential input transition time = 0.6ns (20% to 80%), input voltage

IN+

, V

IN-

) = 0 to V

, LVCMOS/LVTTL inputs = 0 to 3V with 2ns (10% to 90%) transition times, T

= -40°C to +85°C. Typical values

at V

= +3.3V, |V

| = 0.2V, V

= 1.2V, T

= +25°C, unless otherwise noted.) (Notes 3, 4)

Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground

except V

, V

, and ∆V

Note 2: Guaranteed by design and characterization, not production tested.

Note 3: AC parameters are guaranteed by design and characterization.

Note 4: C

includes scope probe and test jig capacitance.

Note 5: t

SET

and t

HOLD

time specify that data must be in a stable state before and after the SEL transition.

Note 6: t

SKEW

is the magnitude difference of differential propagation delay over rated conditions; t

SKEW

= |t

PHLD

- t

PLHD

Note 7: Specification includes test equipment jitter.

MAX9152

800Mbps LVDS/LVPECL-to-LVDS 2 x 2

Crosspoint Switch

_______________________________________________________________________________________ 5

100 300200 400 500 600 700 800

PEAK-TO-PEAK OUTPUT JITTER

AT V

= V

/2 vs. DATA RATE

MAX9152 toc04

DATA RATE (Mbps)

PEAK-TO-PEAK JITTER (ps)

= 0.8V

= 0.4V

= 0.2V

100 300200 400 500 600 700 800

PEAK-TO-PEAK OUTPUT JITTER

AT V

= +1.2V vs. DATA RATE

MAX9152 toc05

DATA RATE (Mbps)

PEAK-TO-PEAK JITTER (ps)

= 0.8V

= 0.4V

= 0.2V

100 400 500200 300 600 700 800

PEAK-TO-PEAK OUTPUT JITTER

AT V

= +3.3V - (V

/2) vs. DATA RATE

MAX9152 toc06

DATA RATE (Mbps)

PEAK-TO-PEAK JITTER (ps)

= 0.8V

= 0.2V

= 0.4V

100 300200 400 500 600 700 800

PEAK-TO-PEAK OUTPUT JITTER

AT V

= +0.4V vs. DATA RATE

MAX9152 toc07

DATA RATE (Mbps)

PEAK-TO-PEAK JITTER (ps)

= 0.8V

= 0.4V

= 0.2V

100 300200 400 500 600 700 800

PEAK-TO-PEAK OUTPUT JITTER

AT V

= +1.6V vs. DATA RATE

MAX9152 toc08

DATA RATE (Mbps)

PEAK-TO-PEAK JITTER (ps)

= 0.8V

= 0.4V

= 0.2V

Typical Operating Characteristics (continued)

= +3.3V, R

= 100Ω, NC/RSEL = high, C

= 5pF, input transition time = 600ps (20% to 80%), V

= 200mV, PRBS = 2

- 1 data

pattern, V

= +1.2V, T

= +25°C, unless otherwise noted.)

Detailed Description

The LVDS interface standard is a signaling method

intended for point-to-point communication over a con-

trolled impedance medium as defined by the ANSI

TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a

lower voltage swing than other common communication

standards, achieving higher data rates with reduced

power consumption while reducing EMI emissions and

system susceptibility to noise.

The MAX9152 is an 800Mbps 2 x 2 crosspoint switch

designed for high-speed, low-power point-to-point and

multidrop interfaces. The device accepts LVDS or dif-

ferential LVPECL signals and routes them to outputs

depending on the selected mode of operation.

A differential input with a magnitude of 0.1V to V

with

single-ended voltage levels at or within the MAX9152's

and ground switches the output. A differential input

with a magnitude of at least 0.15V with single-ended volt-

age levels at or within the MAX9152's V

and ground is

required to meet the AC specifications.

In the 1:2 splitter mode, the outputs repeat the selected

input. This is useful for distributing a signal or creating

a copy for use in protection switching. In the repeater

mode, the device operates as a two-channel buffer.

Repeating restores signal amplitude, allowing isolation

of media segments or longer media drive. The device is

a crosspoint switch where any input can be connected

to any output or outputs. In 2:1 mux mode, primary and

backup signals can be selected to provide a protec-

tion-switched, fault-tolerant application.

MAX9152

800Mbps LVDS/LVPECL-to-LVDS 2 x 2

Crosspoint Switch

6 _______________________________________________________________________________________

Pin Description

PIN NAME FUNCTION

1, 2 SEL1, SEL0 LVCMOS/LVTTL Logic Inputs. Allow the switch to be configured as a mux, repeater, or splitter.

3, 4 IN0+, IN0- LVDS/LVPECL Differential Input 0

Power-Supply Input. Bypass V

to GND with 0.1µF and 0.001µF ceramic capacitors.

6, 7 IN1+, IN1- LVDS/LVPECL Differential Input 1

8 NC/RSEL

Logic Input. Selects differential output resistance. Set NC/RSEL to open or low when R

= 75Ω,

set to high when R

= 100Ω.

9 NC No Connect

10, 11

OUT1-,

OUT1+

LVDS Differential Output 1

12 GND Ground

13, 14

OUT0-,

OUT0+

LVDS Differential Output 0

15, 16 EN1, EN0

LVCMOS/LVTTL Logic Inputs. Enables or disables the outputs. Setting EN0 or EN1 high

enables the corresponding output, OUT0 or OUT1. Setting EN0 or EN1 low puts the

corresponding output into high impedance (differential output resistance is also high

impedance).

1/2 MAX9152

ENABLED

OUT_+

OUT_-

∆V

= V

- V

*

∆V

= V

- V

*

AND V

ARE MEASURED WITH V

= +100mV.

* AND V

* ARE MEASURED WITH V

= -100mV.

= (V

IN_+

) - (V

IN_-

)

IN_+

IN_-

Figure 1. Test Circuit for V

and V

P1-P3 P4-P6 P7-P9 P10-P12

MAX9152EUE+

Mfr. #:

Buy MAX9152EUE+

Manufacturer:

Maxim Integrated

Description:

Analog & Digital Crosspoint ICs LVDS/LVPECL-to-LVDS 2x2 Crosspoint Swtch

Lifecycle:

New from this manufacturer.

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MAX9152EUE+

MAX9152EUE+

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