ISL6745AAUZ-TS2712

7
FN6703.1
September 11, 2008
Pin Descriptions
V
DD
- V
DD
is the power connection for the IC. To optimize
noise immunity, bypass V
DD
to GND with a ceramic
capacitor as close to the V
DD
and GND pins as possible.
The total supply current, I
DD
, will be dependent on the load
applied to outputs OUTA and OUTB. Total I
DD
current is the
sum of the quiescent current and the average output current.
Knowing the operating frequency, F
SW
, and the output
loading capacitance charge, Q, per output, the average
output current can be calculated from Equation 1:
R
TD
- This is the oscillator timing capacitor discharge current
control pin. A resistor is connected between this pin and
GND. The current flowing through the resistor determines
the magnitude of the discharge current. The discharge
current is nominally 55x this current. The PWM deadtime is
determined by the timing capacitor discharge duration.
C
T
- The oscillator timing capacitor is connected between
this pin and GND.
CS - This is the input to the overcurrent protection comparator.
The overcurrent comparator threshold is set at 0.600V nominal.
The CS pin is shorted to GND at the end of each switching
cycle. Depending on the current sensing source impedance, a
series input resistor may be required due to the delay between
the internal clock and the external power switch.
Exceeding the overcurrent threshold will start a delayed
shutdown sequence. Once an overcurrent condition is
detected, the soft-start charge current source is disabled.
The soft-start capacitor begins discharging through a 15µA
current source, and if it discharges to less than 3.9V
(Sustained Overcurrent Threshold), a shutdown condition
occurs and the OUTA and OUTB outputs are forced low.
When the soft-start voltage reaches 0.27V (Reset
Threshold) a soft-start cycle begins.
If the overcurrent condition ceases, and then an additional
50µs period elapses before the shutdown threshold is
reached, no shutdown occurs. The SS charging current is
re-enabled and the soft-start voltage is allowed to recover.
GND - Reference and power ground for all functions on this
device. Due to high peak currents and high frequency
operation, a low impedance layout is necessary. Ground
planes and short traces are highly recommended.
OUTA and OUTB - Alternate half cycle output stages. Each
output is capable of 1A peak currents for driving power
MOSFETs or MOSFET drivers. Each output provides very
low impedance to overshoot and undershoot.
SS - Connect the soft-start timing capacitor between this pin
and GND to control the duration of soft-start. The value of the
capacitor determines the rate of increase of the duty cycle
during start-up, controls the overcurrent shutdown delay, and
the overcurrent and short circuit hiccup restart period.
V
ERR
- The inverting input of the PWM comparator. The
error voltage is applied to this pin to control the duty cycle.
Increasing the signal level increases the duty cycle. The
node may be driven with an external error amplifier or an
opto-coupler.
V
DDP
- V
DDP
is the separate collector supply to the gate
drive. Having a separate V
DDP
pin helps isolate the analog
circuitry from the high power gate drive noise.
Functional Description
Features
The ISL6745A PWM is an excellent choice for low cost
bridge topologies for applications requiring accurate
frequency and deadtime control. Among its many features
are 1A FET drivers, adjustable soft-start, overcurrent
protection and internal thermal protection, allowing a highly
flexible design with minimal external components.
Oscillator
The ISL6745A has an oscillator with a frequency range to
2MHz, programmable using a resistor R
TD
and capacitor C
T
.
The switching period may be considered to be the sum of
the timing capacitor charge and discharge durations. The
charge duration is determined by C
T
and the internal current
source (assumed to be 16
A in the formula). The discharge
duration is determined by R
TD
and C
T
.
where T
C
and T
D
are the approximate charge and discharge
times, respectively, T
OSC
is the oscillator free running
period, and F
OSC
is the oscillator frequency. One output
switching cycle requires two oscillator cycles. The actual
times will be slightly longer than calculated due to internal
propagation delays of approximately 5ns/transition. This
delay adds directly to the switching duration, and also
causes overshoot of the timing capacitor peak and valley
voltage thresholds, effectively increasing the peak-to-peak
voltage on the timing capacitor. Additionally, if very low
charge and discharge currents are used, there will be an
increased error due to the input impedance at the C
T
pin.
The above formulae help with the estimation of the
frequency. Practically, effects like stray capacitances that
affect the overall C
T
capacitance, variation in R
TD
voltage
and charge current over-temperature, etc. exist, and are
best evaluated in-circuit. Equation 2 follows from the basic
capacitor current equation, . In this case, with
(EQ. 1)
I
OUT
2QF
SW
= A
T
C
1.25
4
×10 C
T
s
(EQ. 2)
T
D
1
CTDisch eCurrentGainarg
-----------------------------------------------------------------------------
R
TD
C
T
s
(EQ. 3)
T
OSC
T
C
T
D
+
1
F
OSC
----------------
== s(EQ. 4)
iC
td
dV
×=
ISL6745A
8
FN6703.1
September 11, 2008
variation in dV with R
TD
(Figure 5), and in charge current
(Figure 4), results from Equation 2 would differ from the
calculated frequency. The typical performance curves may
be used as a tool along with the previous equations as a
more accurate tool to estimate the operating frequency more
accurately.
The maximum duty cycle, D, and deadtime, DT, can be
calculated from:
Soft-Start Operation
The ISL6745A features a soft-start using an external
capacitor in conjunction with an internal current source.
Soft-start reduces stresses and surge currents during
start-up.
The oscillator capacitor signal, C
T
, is compared to the
soft-start voltage, SS, in the SS comparator which drives the
PWM latch. While the SS voltage is less than 3.5V, duty
cycle is limited. The output pulse width increases as the
soft-start capacitor voltage increases up to 3.5V. This has
the effect of increasing the duty cycle from zero to the
maximum pulse width during the soft-start period. When the
soft-start voltage exceeds 3.5V, soft-start is completed.
Soft-start occurs during start-up and after recovery from an
overcurrent shutdown. The soft-start voltage is clamped to 4V.
Gate Drive
The ISL6745A is capable of sourcing and sinking 1A peak
current, and may also be used in conjunction with a
MOSFET driver such as the ISL6700 for level shifting. To
limit the peak current through the IC, an external resistor
may be placed between the totem-pole output of the IC
(OUTA or OUTB pin) and the gate of the MOSFET. This
small series resistor also damps any oscillations caused by
the resonant tank of the parasitic inductances in the traces of
the board and the FET’s input capacitance.
Overcurrent Operation
Overcurrent delayed shutdown is enabled once the soft-start
cycle is complete. If an overcurrent condition is detected, the
soft-start charging current source is disabled and the
soft-start capacitor is allowed to discharge through a 15µA
source. At the same time a 50µs retriggerable one-shot timer
is activated. It remains active for 50µs after the overcurrent
condition ceases. If the soft-start capacitor discharges to
3.9V, the output is disabled. This state continues until the
soft-start voltage reaches 270mV, at which time a new
soft-start cycle is initiated. If the overcurrent condition stops
at least 50µs prior to the soft-start voltage reaching 3.9V, the
soft-start charging currents revert to normal operation and
the soft-start voltage is allowed to recover.
Thermal Protection
An internal temperature sensor protects the device should
the junction temperature exceed +145°C. There is
approximately +15°C of hysteresis.
Ground Plane Requirements
Careful layout is essential for satisfactory operation of the
device. A good ground plane must be employed. V
DD
should
be bypassed directly to GND with good high frequency
capacitance.
DT
C
T
OSC
= (EQ. 5)
DT 1 D()T
OSC
= s(EQ. 6)
ISL6745A
9
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FN6703.1
September 11, 2008
ISL6745AISL6745A
Mini Small Outline Plastic Packages (MSOP)
NOTES:
1. These package dimensions are within allowable dimensions of
JEDEC MO-187BA.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs and are measured at Datum Plane. Mold flash, protrusion
and gate burrs shall not exceed 0.15mm (0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions
and are measured at Datum Plane. Interlead flash and
protrusions shall not exceed 0.15mm (0.006 inch) per side.
5. Formed leads shall be planar with respect to one another within
0.10mm (.004) at seating Plane.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08mm (0.003 inch) total in excess
of “b” dimension at maximum material condition. Minimum space
between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Datums and to be determined at Datum plane
.
11. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are for reference only
L
0.25
(0.010)
L1
R1
R
4X θ
4X θ
GAUGE
PLANE
SEATING
PLANE
EE1
N
12
TOP VIEW
INDEX
AREA
-C-
-B-
0.20 (0.008) A
B
C
SEATING
PLANE
0.20 (0.008) C
0.10 (0.004) C
-A-
-H-
SIDE VIEW
b
e
D
A
A1
A2
-B-
END VIEW
0.20 (0.008) C
D
E
1
C
L
C
a
- H -
-A -
- B -
- H -
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.037 0.043 0.94 1.10 -
A1 0.002 0.006 0.05 0.15 -
A2 0.030 0.037 0.75 0.95 -
b 0.007 0.011 0.18 0.27 9
c 0.004 0.008 0.09 0.20 -
D 0.116 0.120 2.95 3.05 3
E1 0.116 0.120 2.95 3.05 4
e 0.020 BSC 0.50 BSC -
E 0.187 0.199 4.75 5.05 -
L 0.016 0.028 0.40 0.70 6
L1 0.037 REF 0.95 REF -
N10 107
R 0.003 - 0.07 - -
R1 0.003 - 0.07 - -
5
o
15
o
5
o
15
o
-
α
0
o
6
o
0
o
6
o
-
Rev. 0 12/02
θ

ISL6745AAUZ-TS2712

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers SEGREGATE FOR ADAPTER PROJECT
Lifecycle:
New from this manufacturer.
Delivery:
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