1
Features
4.5V to 5.5V Read/Write
Access Time – 90 ns
Sector Erase Architecture
Thirty 32K Word (64K byte) Sectors with Individual Write Lockout
Eight 4K Word (8K byte) Sectors with Individual Write Lockout
Two 16K Word (32K byte) Sectors with Individual Write Lockout
Fast Word Program Time – 10 µs
Fast Sector Erase Time – 200 ms
Dual-plane Organization, Permitting Concurrent Read while Program/Erase
Memory Plane A: Eight 4K Word, Two 16K Word and Six 32K Word Sectors
Memory Plane B: Twenty-four 32K Word Sectors
Erase Suspend Capability
Supports Reading/Programming Data from Any Sector by Suspending Erase of
Any Different Sector
Low-power Operation
–60 mA Active
3 mA Standby
DATA Polling, Toggle Bit, Ready/Busy for End of Program Detection
RESET Input for Device Initialization
Sector Program Unlock Command
TSOP, CBGA and µBGA Package Options
Top or Bottom Boot Block Configuration Available
Description
The AT49F16X4(T) is a 5.0-volt 16-megabit Flash memory organized as 1,048,576
words of 16 bits each or 2,097,152 bytes of 8 bits each. The x16 data appears on
I/O0 - I/O15; the x8 data appears on I/O0 - I/O7. The memory is divided into 40 sec-
tors for erase operations. The device is offered in 48-lead TSOP and 48-ball µBGA
packages. The device has CE
and OE control signals to avoid any bus contention.
This device can be read or reprogrammed using a single 5.0V power supply, making it
ideally suited for in-system programming.
The device powers on in the read mode. Command sequences are used to place the
device in other operation modes such as program and erase. The device has the
Rev. 0977J–04/00
16-megabit
(1M x 16/2M x 8)
5-volt Only
Flash Memory
AT49F1604
AT49F1604T
AT49F1614
AT49F1614T
Not Recommended for
New Designs
Pin Configurations
Pin Name Function
A0 - A19 Addresses
CE
Chip Enable
OE
Output Enable
WE
Write Enable
RESET Reset
RDY/BUSY
READY/BUSY Output
I/O0 - I/O14 Data Inputs/Outputs
I/O15 (A-1)
I/O15 (Data Input/Output, Word Mode)
A-1 (LSB Address Input, Byte Mode)
BYTE
Selects Byte or Word Mode
NC No Connect
DC Don’t Connect
(continued)
AT49F1604(T)/1614(T)
2
capability to protect the data in any sector. Once the data
protection for a given sector is enabled, the data in that
sector cannot be changed using input levels between
ground and V
CC
.
The device is segmented into two memory planes. Reads
from memory plane B may be performed even while pro-
gram or erase functions are being executed in memory
plane A and vice versa. This operation allows improved
system performance by not requiring the system to wait for
a program or erase operation to complete before a read is
performed. To further increase the flexibility of the device, it
contains an Erase Suspend feature. This feature will put
the erase on hold for any amount of time and let the user
read data from or program data to any of the remaining
sectors within the same memory plane. There is no reason
to suspend the erase operation if the data to be read is in
the other memory plane. The end of a program or an erase
cycle is detected by the Ready/Busy
pin, Data Polling or by
the toggle bit.
A six-byte command (Bypass Unlock) sequence to remove
the requirement of entering the three-byte program
sequence is offered to further improve programming time.
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
NC
NC
WE
RESET
NC
NC
A19
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
VCC
GND
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
CBGA Top View
RDY/BUSY
NC
A18
NC
I/O2
I/O10
I/O11
I/O3
A3
A4
A2
A1
A0
CE
OE
VSS
A7
A17
A6
A5
I/O0
I/O8
I/O9
I/O1
WE
RESET
NC
A19
I/O5
I/O12
VCC
I/O4
A9
A8
A10
A11
I/O7
I/O14
I/O13
I/O6
A13
A12
A14
A15
A16
BYTE
I/O15
VSS
A
B
C
D
E
F
G
H
1
23456
/A-1
µBGA Top View (Ball Down)
A
B
C
D
E
F
1
234567
A13
A14
A15
A16
VCC
GND
A11
A10
A12
I/O14
I/O15
I/O7
A8
WE
A9
I/O5
I/O6
I/O13
NC
RST
I/O11
I/O12
I/O4
A18
I/O2
I/O3
VCC
A19
A17
A6
I/O8
I/O9
I/O10
A7
A5
A3
CE
I/O0
I/O1
A4
A2
A1
A0
GND
OE
8
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
RESET
NC
NC
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
AT49F1604(T)
AT49F1614(T)
AT49F1604(T)/1614(T)
3
After entering the six-byte code, only single pulses on the
write control lines are required for writing into the device.
This mode (Single Pulse Byte/Word Program) is exited by
powering down the device or by pulsing the RESET
pin low
for a minimum of 50 ns and then bringing it back to V
CC
.
Erase and Erase Suspend/Resume commands will not
work while in this mode; if entered, they will result in data
being programmed into the device. It is not recommended
that the six-byte code reside in the software of the final
product but only exist in external programming code.
For the AT49BV1614(T), the BYTE
pin controls whether
the device data I/O pins operate in the byte or word config-
uration. If the BYTE
pin is set at logic 1, the device is in
word configuration, I/O0 - I/O15 are active and controlled
by CE
and OE.
If the BYTE pin is set at logic 0, the device is in byte con-
figuration, and only data I/O pins I/O0 - I/O7 are active and
controlled by CE
and OE. The data I/O pins I/O8 - I/O14
are tri-stated, and the I/O15 pin is used as an input for the
LSB (A-1) address function.
Block Diagram
Device Operation
READ: The AT49F16X4(T) is accessed like an EPROM.
When CE
and OE are low and WE is high, the data stored
at the memory location determined by the address pins are
asserted on the outputs. The outputs are put in the high-
impedance state whenever CE
or OE is high. This dual-line
control gives designers flexibility in preventing bus
contention.
COMMAND SEQUENCES: When the device is first pow-
ered on it will be reset to the read or standby mode,
depending upon the state of the control line inputs. In order
to perform other device functions, a series of command
sequences are entered into the device. The command
sequences are shown in the Command Definitions table on
page 6 (I/O8 - I/O15 are dont care inputs for the command
codes). The command sequences are written by applying a
IDENTIFIER
REGISTER
STATUS
REGISTER
DATA
COMPARATOR
OUTPUT
MULTIPLEXER
OUTPUT
BUFFER
INPUT
BUFFER
COMMAND
REGISTER
DATA
REGISTER
Y-GATING
WRITE STATE
MACHINE
PROGRAM/ERASE
VOLTAGE SWITCH
CE
WE
OE
RESET
BYTE
RDY/BUSY
VCC
GND
Y-DECODER
X-DECODER
INPUT
BUFFER
ADDRESS
LATCH
I/O0 - I/O15/A-1
A0 - A19
PLANE B
SECTORS
PLANE A SECTORS

AT49F1614T-90TC

Mfr. #:
Manufacturer:
Description:
IC FLASH 16M PARALLEL 48TSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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