74LVT240
3.3 V Octal inverting buffer/line driver; 3-state
Rev. 3 — 10 April 2017 Product data sheet
1 General description
The 74LVT240 is a high-performance BiCMOS product designed for V
CC
operation at
3.3 V.
This device is an octal inverting buffer that is ideal for driving bus lines. The device
features two output enable pins (1OE, 2OE), each controlling four of the 3-State outputs.
2 Features and benefits
Octal bus interface
3-state buffers
Output capability: +64 mA and -32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus hold data inputs eliminate need for external pull-up resistors to hold unused inputs
Live insertion and extraction permitted
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection
JESD78 Class II exceeds 500 mA
ESD protection:
MIL STD 883 method 3015: exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
3 Ordering information
Table 1. Ordering information
PackageType number
Temperature range Name Description Version
74LVT240D -40 °C to +85 °C SO20 plastic small outline package; 20 leads;
body width 7.5 mm
SOT163-1
74LVT240DB -40 °C to +85 °C SSOP20 plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74LVT240PW -40 °C to +85 °C TSSOP20 plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT360-1
Nexperia
74LVT240
3.3 V Octal inverting buffer/line driver; 3-state
74LVT240 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 10 April 2017
2 / 15
4 Functional diagram
aaa-026569
1Y0 182 1A0
2Y0 911 2A0
1Y1 164 1A1
2Y1 713 2A1
1Y2 146 1A2
2Y2 515 2A2
1Y3 128 1A3
2Y3 317 2A3
1 1OE
19 2OE
Figure 1. Logic symbol
aaa-026570
1
EN
18
2
4
6
8
16
14
12
19
EN
9
11
13
15
17
7
5
3
Figure 2. IEC logic symbol
5 Pinning information
5.1 Pinning
74LVT240
1OE V
CC
1A0 2OE
2Y3 1Y0
1A1 2A3
2Y2 1Y1
1A2 2A2
2Y1 1Y2
1A3 2A1
2Y0 1Y3
GND 2A0
aaa-026571
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Figure 3. Pin configuration for SO20
74LVT240
1OE V
CC
1A0 2OE
2Y3 1Y0
1A1 2A3
2Y2 1Y1
1A2 2A2
2Y1 1Y2
1A3 2A1
2Y0 1Y3
GND 2A0
aaa-026572
1
2
3
4
5
6
7
8
9
10
12
11
14
13
16
15
18
17
20
19
Figure 4. Pin configuration for (T)SSOP20
Nexperia
74LVT240
3.3 V Octal inverting buffer/line driver; 3-state
74LVT240 All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2017. All rights reserved.
Product data sheet Rev. 3 — 10 April 2017
3 / 15
5.2 Pin description
Table 2. Pin description
Symbol Pin Description
1OE, 2OE 1, 19 output enable input (active LOW)
1A0, 1A1, 1A2, 1A3 2, 4, 6, 8 data input
2Y0, 2Y1, 2Y2, 2Y3 9, 7, 5, 3 bus output
GND 10 ground (0 V)
2A0, 2A1, 2A2, 2A3 11, 13, 15, 17 data input
1Y0, 1Y1, 1Y2, 1Y3 18, 16, 14, 12 bus output
V
CC
20 supply voltage
6 Functional description
Table 3. Function table
[1]
Inputs Outputs
nOE nAn nYn
L L H
L H L
H X Z
[1] H = HIGH voltage level;
L = LOW voltage level;
X = don’t care;
Z = high-impedance OFF-state.

74LVT240PW/AUJ

Mfr. #:
Manufacturer:
Nexperia
Description:
Buffers & Line Drivers ABT octal inverting buffer
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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