MT89L86 Data Sheet
29
Zarlink Semiconductor Inc.
† Timing is over recommended temperature & power supply voltages.
‡ Typical figures are at 25
C and are for design aid only: not guaranteed and not subject to production testing.
* High Impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to discharge C
L
.
Figure 17 - Serial Outputs and External Control
Figure 18 - Output Driver Enable
AC Electrical Characteristics
†
- Serial Streams for ST-BUS and GCI Backplanes (2.048 Mb/s)
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
1
O
U
T
P
U
T
S
STo0/9 Delay - Active to High Z
t
SAZ
55 ns R
L
=1 K*, C
L
=150 pF
2 STo0/9 Delay - High Z to Active t
SZA
55 ns C
L
=150 pF
3 Output Driver Enable Delay t
OED
50 ns R
L
=1 K*, C
L
=150 pF
4 CSTo Output Delay t
XCD
55 ns C
L
=150 pF
CSTo
CLK
STo0
to
STo9
STo0
to
STo9
Bit Cell Boundary
(GCI)
(ST-BUS)
*
t
SAZ
t
SZA
t
XCD
*
V
HM
V
LM
V
HM
V
LM
V
HM
V
LM
V
HM
V
LM
ODE
STo0
to
STo9
V
HM
V
LM
V
HM
V
LM
t
OED
*
*
t
OED
