IDT8T49N366AASGI REVISION A JUNE 28, 2013 28 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
2.5V LVPECL Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T49N366I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T49N366I is the sum of the core power plus the output power dissipated due to the load.
The following is the power dissipation for V
CC
= 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
Power (core)
MAX
= V
CC_MAX
* I
EE_MAX
= 2.625V * 880mA = 2310W
Power (outputs)
MAX
= 33.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 33.2mW = 199.2mW
Total Power_
MAX
(2.625V, with all outputs switching) = 2310mW + 199.2mW = 2509.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 12.4°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 2.509W * 12.4°C/W = 116.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 8.
JA
vs. Air FlowTable for an 80-Ball CABGA
NOTE 1:
JA
simulation is performed with 8-layers, 8in. x 8in. PCB for the 10x10, 1mm ball pitch BGA package.
JA
vs. Air Flow
Meters per Second 0 1 2 3
Multi-Layer PCB, NOTE 1 12.4°C/W 11°C/W 10.3°C/W 10°C/W
IDT8T49N366AASGI REVISION A JUNE 28, 2013 29 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
3. Calculations and Equations.
The purpose of this section is to calculate the power dissipation for the LVPECL output pairs.
LVPECL output driver circuit and termination are shown in Figure 9.
Figure 9. LVPECL Driver Circuit and Termination
To calculate power dissipation per output pair due to the load, use the following equations which assume a 50 load, and a termination
voltage of V
CCO
– 2V.
For logic high, V
OUT
= V
OH_MAX
= V
CCO_MAX
– 0.7V
(V
CCO_MAX
– V
OH_MAX
) = 0.7V
For logic low, V
OUT
= V
OL_MAX
= V
CCO_MAX
1.5V
(V
CCO_MAX
– V
OL_MAX
) = 1.5V
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
OH_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) = [(2V – (V
CCO_MAX
– V
OH_MAX
))/R
L
] * (V
CCO_MAX
– V
OH_MAX
) =
[(2V – 0.7V)/50] * 0.7V = 18.2mW
Pd_L = [(V
OL_MAX
– (V
CCO_MAX
– 2V))/R
L
] * (V
CCO_MAX
– V
OL_MAX
) = [(2V – (V
CCO_MAX
– V
OL_MAX
))/R
L]
* (V
CCO_MAX
– V
OL_MAX
) =
[(2V – 1.5V)/50] * 1.5V = 15mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 33.2mW
V
OUT
V
CCO
V
CCO
- 2V
Q1
RL
50Ω
IDT8T49N366AASGI REVISION A JUNE 28, 2013 30 ©2013 Integrated Device Technology, Inc.
IDT8T49N366I Data Sheet FEMTOCLOCK
®
NG TRIPLE UNIVERSAL FREQUENCY TRANSLATOR
TM
LVDS Power Considerations
This section provides information on power dissipation and junction temperature for the IDT8T49N366I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the IDT8T49N366I is the sum of the core power plus the analog power plus the output power dissipated due to
loading. The following is the power dissipation for V
CC
= 2.5V + 5% = 2.625V, which gives worst case results.
Power (core)
MAX
= V
CC_MAX
* (I
CC_MAXl
+ I
CCA_MAX
) = 2.625V * (750mA + 78mA) = 2173.5mW
Power (outputs)
MAX
= V
CCO_MAX
* I
CCO_MAX
= 2.625V * 128mA = 336mW
Total Power_
MAX
= 2173.5mW + 336mW = 2509.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 12.4°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 2.510W * 12.4°C/W = 116.1°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 9.
JA
vs. Air FlowTable for an 80-Ball CABGA
NOTE 1:
JA
simulation is performed with 8-layers, 8in. x 8in. PCB for the 10x10, 1mm ball pitch BGA package.
JA
vs. Air Flow
Meters per Second 0 1 2 3
Multi-Layer PCB, NOTE 1 12.4°C/W 11°C/W 10.3°C/W 10°C/W

8T49N366A-000ASGI

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IDT
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Clock Generators & Support Products Femto NG Clock Generator
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