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ADV7181CBCPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
ADV7181C
Rev. A | Page 7 of 20
ANALOG SPECIFICATIONS
AVDD = 3.1.5 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T
MIN
to T
MAX
= −40°C to +85°C,
unless otherwise noted. Recommended analog input video signal range: 0.5 V to 1.6 V, typically 1 V p-p.
Table 4.
Parameter
1, 2
Test Conditions Min Typ Max Unit
CLAMP CIRCUITRY
External Clamp Capacitor 0.1 μF
Input Impedance; Except Pin 34 (FB) Clamps switched off 10 MΩ
Input Impedance of Pin 34 (FB) 20 kΩ
CML 1.86 V
ADC Full-Scale Level CML + 0.8 V V
ADC Zero-Scale level CML − 0.8 V V
ADC Dynamic Range 1.6 V
Clamp Level (When Locked) CVBS input CML – 0.292 V V
SCART RGB input (R, G, B signals) CML – 0.4 V V
S-Video input (Y signal) CML – 0.292 V V
S-Video input (C signal) CML – 0 V V
Component input (Y, Pr, Pb signals) CML – 0.3 V V
PC RGB input (R, G, B signals) CML – 0.3 V V
Large Clamp Source Current SDP only 0.75 mA
Large Clamp Sink Current SDP only 0.9 mA
Fine Clamp Source Current SDP only 17 μA
Fine Clamp Sink Current SDP only 17 μA
1
The minimum/maximum specifications are guaranteed over this range.
2
Guaranteed by characterization.
ADV7181C
Rev. A | Page 8 of 20
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
AVDD to AGND 4 V
DVDD to DGND 2.2 V
PVDD to AGND 2.2 V
DVDDIO to DGND 4 V
DVDDIO to AVDD −0.3 V to +0.3 V
PVDD to DVDD −0.3 V to +0.3 V
DVDDIO to PVDD −0.3 V to +2 V
DVDDIO to DVDD −0.3 V to +2 V
AVDD to PVDD −0.3 V to +2 V
AVDD to DVDD −0.3 V to +2 V
Digital Inputs Voltage to DGND
DGND − 0.3 V to
DVDDIO + 0.3 V
Digital Outputs Voltage to DGND
DGND − 0.3 V to
DVDDIO + 0.3 V
Analog Inputs to AGND
AGND − 0.3 V to
AVDD + 0.3 V
Operating Temperature −40°C to +85°C
Maximum Junction Temperature (T
J MAX
) 125°C
Storage Temperature Range −65°C to +150°C
Infrared Reflow Soldering (20 sec) 260°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
PACKAGE THERMAL PERFORMANCE
To reduce power consumption when using the part the user is
advised to turn off any unused ADCs.
It is imperative that the recommended scripts be used for the
following high current modes: SCART, 720p, 1080i, and all
RGB graphic standards. Using the recommended scripts ensures
correct thermal performance. These scripts are available from
a local FAE.
For optimum thermal performance of the LFCSP_VQ package,
ensure that the exposed paddle is soldered to ground.
ESD CAUTION
ADV7181C
Rev. A | Page 9 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
VS
63
FIELD/DE
62
P16
61
P17
60
P18
59
P19
58
DVDD
57
DGND
56
HS_IN/CS_IN
55
VS_IN
54
SCLK
53
SDATA
52
ALSB
51
RESET
50
SOG/SOY
49
A
IN
6
47
A
IN
4
46
A
IN
3
45
NC
42
CML
43
AGND
44
CAPC2
48
A
IN
5
41
REFOUT
40
AVDD
39
CAPY2
37
AGND
36
A
IN
2
35
A
IN
1
34
FB
33
NC
38
CAPY1
2
HS/CS
3
DGND
4
DVDDIO
7
P13
6
P14
5
P15
1
INT
8
P12
9
SFL/SYNC_OUT
10
DGND
12
P11
13
P10
14
P9
15
P8
16
P7
11
DVDDIO
17
P6
18
P5
19
P4
20
LLC
21
XTAL1
22
XTAL
23
DVDD
24
DGND
25
P3
26
P2
27
P1
28
P0
29
PWRDWN
30
ELPF
31
PVDD
32
AGND
PIN 1
ADV7181C
TOP VIEW
(Not to Scale)
07513-002
NOTES
1. NC = NO CONNECT.
2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
Figure 2. Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
3, 10, 24, 57 DGND G Digital Ground.
32, 37, 43 AGND G Analog Ground.
4, 11 DVDDIO P Digital I/O Supply Voltage (3.3 V).
23, 58 DVDD P Digital Core Supply Voltage (1.8 V).
40 AVDD P Analog Supply Voltage (3.3 V).
31 PVDD P PLL Supply Voltage (1.8 V).
34 FB I Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
35, 36, 46, 47, 48, 49 A
IN
1 to A
IN
6 I Analog Video Input Channels.
28 to 25, 19 to 12,
8 to 5, 62 to 59
P0 to P19 O Video Pixel Output Port. Refer to Table 9 for output configuration modes.
1
INT
O
Interrupt. This pin can be active low or active high. When SDP/CP status bits
change, this pin is triggered. The set of events that triggers an interrupt is
under user control.
2 HS/CS O
HS: Horizontal Synchronization Output Signal (SDP and CP Modes).
CS: Digital Composite Synchronization Signal (CP Mode).
64 VS O Vertical Synchronization Output Signal (SDP and CP Modes).
63 FIELD/DE O
Field Synchronization Output Signal (All Interlaced Video Modes). This pin also
can be enabled as an data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
53 SDATA I/O I
2
C Port Serial Data Input/Output Pin.
54 SCLK I I
2
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
52 ALSB I
This pin selects the I
2
C address for the ADV7181C control and VBI readback
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

ADV7181CBCPZ

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Manufacturer:
Analog Devices Inc.
Description:
IC VIDEO DECODER LFCSP
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